| /* |
| * Copyright (C) 2014 Alexander Shiyan <shc_work@mail.ru> |
| * |
| * The code contained herein is licensed under the GNU General Public |
| * License. You may obtain a copy of the GNU General Public License |
| * Version 2 or later at the following locations: |
| * |
| * http://www.opensource.org/licenses/gpl-license.html |
| * http://www.gnu.org/copyleft/gpl.html |
| */ |
| |
| /dts-v1/; |
| #include "imx27.dtsi" |
| |
| / { |
| model = "Eukrea CPUIMX27"; |
| compatible = "eukrea,cpuimx27", "fsl,imx27"; |
| |
| memory { |
| reg = <0xa0000000 0x04000000>; |
| }; |
| |
| clocks { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| compatible = "simple-bus"; |
| |
| clk14745600: clock@0 { |
| #clock-cells = <0>; |
| compatible = "fixed-clock"; |
| clock-frequency = <14745600>; |
| reg = <0>; |
| }; |
| }; |
| }; |
| |
| &fec { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_fec>; |
| status = "okay"; |
| }; |
| |
| &i2c1 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_i2c1>; |
| status = "okay"; |
| |
| pcf8563@51 { |
| compatible = "nxp,pcf8563"; |
| reg = <0x51>; |
| }; |
| }; |
| |
| &nfc { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_nfc>; |
| nand-bus-width = <8>; |
| nand-ecc-mode = "hw"; |
| nand-on-flash-bbt; |
| status = "okay"; |
| }; |
| |
| &owire { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_owire>; |
| status = "okay"; |
| }; |
| |
| &sdhci2 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_sdhc2>; |
| bus-width = <4>; |
| non-removable; |
| status = "okay"; |
| }; |
| |
| &uart4 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_uart4>; |
| fsl,uart-has-rtscts; |
| status = "okay"; |
| }; |
| |
| &usbh2 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_usbh2>; |
| dr_mode = "host"; |
| phy_type = "ulpi"; |
| disable-over-current; |
| status = "okay"; |
| }; |
| |
| &usbotg { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_usbotg>; |
| dr_mode = "otg"; |
| phy_type = "ulpi"; |
| disable-over-current; |
| status = "okay"; |
| }; |
| |
| &weim { |
| status = "okay"; |
| |
| nor: nor@0,0 { |
| #address-cells = <1>; |
| #size-cells = <1>; |
| compatible = "cfi-flash"; |
| reg = <0 0x00000000 0x04000000>; |
| bank-width = <2>; |
| linux,mtd-name = "physmap-flash.0"; |
| fsl,weim-cs-timing = <0x00008f03 0xa0330d01 0x002208c0>; |
| }; |
| |
| uart8250@3,200000 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_uart8250_1>; |
| compatible = "ns8250"; |
| clocks = <&clk14745600>; |
| fsl,weim-cs-timing = <0x0000d603 0x0d1d0d01 0x00d20000>; |
| interrupts = <&gpio2 23 IRQ_TYPE_LEVEL_LOW>; |
| reg = <3 0x200000 0x1000>; |
| reg-shift = <1>; |
| reg-io-width = <1>; |
| no-loopback-test; |
| }; |
| |
| uart8250@3,400000 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_uart8250_2>; |
| compatible = "ns8250"; |
| clocks = <&clk14745600>; |
| fsl,weim-cs-timing = <0x0000d603 0x0d1d0d01 0x00d20000>; |
| interrupts = <&gpio2 22 IRQ_TYPE_LEVEL_LOW>; |
| reg = <3 0x400000 0x1000>; |
| reg-shift = <1>; |
| reg-io-width = <1>; |
| no-loopback-test; |
| }; |
| |
| uart8250@3,800000 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_uart8250_3>; |
| compatible = "ns8250"; |
| clocks = <&clk14745600>; |
| fsl,weim-cs-timing = <0x0000d603 0x0d1d0d01 0x00d20000>; |
| interrupts = <&gpio2 27 IRQ_TYPE_LEVEL_LOW>; |
| reg = <3 0x800000 0x1000>; |
| reg-shift = <1>; |
| reg-io-width = <1>; |
| no-loopback-test; |
| }; |
| |
| uart8250@3,1000000 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_uart8250_4>; |
| compatible = "ns8250"; |
| clocks = <&clk14745600>; |
| fsl,weim-cs-timing = <0x0000d603 0x0d1d0d01 0x00d20000>; |
| interrupts = <&gpio2 30 IRQ_TYPE_LEVEL_LOW>; |
| reg = <3 0x1000000 0x1000>; |
| reg-shift = <1>; |
| reg-io-width = <1>; |
| no-loopback-test; |
| }; |
| }; |
| |
| &iomuxc { |
| imx27-eukrea-cpuimx27 { |
| pinctrl_fec: fecgrp { |
| fsl,pins = < |
| MX27_PAD_SD3_CMD__FEC_TXD0 0x0 |
| MX27_PAD_SD3_CLK__FEC_TXD1 0x0 |
| MX27_PAD_ATA_DATA0__FEC_TXD2 0x0 |
| MX27_PAD_ATA_DATA1__FEC_TXD3 0x0 |
| MX27_PAD_ATA_DATA2__FEC_RX_ER 0x0 |
| MX27_PAD_ATA_DATA3__FEC_RXD1 0x0 |
| MX27_PAD_ATA_DATA4__FEC_RXD2 0x0 |
| MX27_PAD_ATA_DATA5__FEC_RXD3 0x0 |
| MX27_PAD_ATA_DATA6__FEC_MDIO 0x0 |
| MX27_PAD_ATA_DATA7__FEC_MDC 0x0 |
| MX27_PAD_ATA_DATA8__FEC_CRS 0x0 |
| MX27_PAD_ATA_DATA9__FEC_TX_CLK 0x0 |
| MX27_PAD_ATA_DATA10__FEC_RXD0 0x0 |
| MX27_PAD_ATA_DATA11__FEC_RX_DV 0x0 |
| MX27_PAD_ATA_DATA12__FEC_RX_CLK 0x0 |
| MX27_PAD_ATA_DATA13__FEC_COL 0x0 |
| MX27_PAD_ATA_DATA14__FEC_TX_ER 0x0 |
| MX27_PAD_ATA_DATA15__FEC_TX_EN 0x0 |
| >; |
| }; |
| |
| pinctrl_i2c1: i2c1grp { |
| fsl,pins = < |
| MX27_PAD_I2C_DATA__I2C_DATA 0x0 |
| MX27_PAD_I2C_CLK__I2C_CLK 0x0 |
| >; |
| }; |
| |
| pinctrl_nfc: nfcgrp { |
| fsl,pins = < |
| MX27_PAD_NFRB__NFRB 0x0 |
| MX27_PAD_NFCLE__NFCLE 0x0 |
| MX27_PAD_NFWP_B__NFWP_B 0x0 |
| MX27_PAD_NFCE_B__NFCE_B 0x0 |
| MX27_PAD_NFALE__NFALE 0x0 |
| MX27_PAD_NFRE_B__NFRE_B 0x0 |
| MX27_PAD_NFWE_B__NFWE_B 0x0 |
| >; |
| }; |
| |
| pinctrl_owire: owiregrp { |
| fsl,pins = < |
| MX27_PAD_RTCK__OWIRE 0x0 |
| >; |
| }; |
| |
| pinctrl_sdhc2: sdhc2grp { |
| fsl,pins = < |
| MX27_PAD_SD2_CLK__SD2_CLK 0x0 |
| MX27_PAD_SD2_CMD__SD2_CMD 0x0 |
| MX27_PAD_SD2_D0__SD2_D0 0x0 |
| MX27_PAD_SD2_D1__SD2_D1 0x0 |
| MX27_PAD_SD2_D2__SD2_D2 0x0 |
| MX27_PAD_SD2_D3__SD2_D3 0x0 |
| >; |
| }; |
| |
| pinctrl_uart4: uart4grp { |
| fsl,pins = < |
| MX27_PAD_USBH1_TXDM__UART4_TXD 0x0 |
| MX27_PAD_USBH1_RXDP__UART4_RXD 0x0 |
| MX27_PAD_USBH1_TXDP__UART4_CTS 0x0 |
| MX27_PAD_USBH1_FS__UART4_RTS 0x0 |
| >; |
| }; |
| |
| pinctrl_uart8250_1: uart82501grp { |
| fsl,pins = < |
| MX27_PAD_USB_PWR__GPIO2_23 0x0 |
| >; |
| }; |
| |
| pinctrl_uart8250_2: uart82502grp { |
| fsl,pins = < |
| MX27_PAD_USBH1_SUSP__GPIO2_22 0x0 |
| >; |
| }; |
| |
| pinctrl_uart8250_3: uart82503grp { |
| fsl,pins = < |
| MX27_PAD_USBH1_OE_B__GPIO2_27 0x0 |
| >; |
| }; |
| |
| pinctrl_uart8250_4: uart82504grp { |
| fsl,pins = < |
| MX27_PAD_USBH1_RXDM__GPIO2_30 0x0 |
| >; |
| }; |
| |
| pinctrl_usbh2: usbh2grp { |
| fsl,pins = < |
| MX27_PAD_USBH2_CLK__USBH2_CLK 0x0 |
| MX27_PAD_USBH2_DIR__USBH2_DIR 0x0 |
| MX27_PAD_USBH2_NXT__USBH2_NXT 0x0 |
| MX27_PAD_USBH2_STP__USBH2_STP 0x0 |
| MX27_PAD_CSPI2_SCLK__USBH2_DATA0 0x0 |
| MX27_PAD_CSPI2_MOSI__USBH2_DATA1 0x0 |
| MX27_PAD_CSPI2_MISO__USBH2_DATA2 0x0 |
| MX27_PAD_CSPI2_SS1__USBH2_DATA3 0x0 |
| MX27_PAD_CSPI2_SS2__USBH2_DATA4 0x0 |
| MX27_PAD_CSPI1_SS2__USBH2_DATA5 0x0 |
| MX27_PAD_CSPI2_SS0__USBH2_DATA6 0x0 |
| MX27_PAD_USBH2_DATA7__USBH2_DATA7 0x0 |
| >; |
| }; |
| |
| pinctrl_usbotg: usbotggrp { |
| fsl,pins = < |
| MX27_PAD_USBOTG_CLK__USBOTG_CLK 0x0 |
| MX27_PAD_USBOTG_DIR__USBOTG_DIR 0x0 |
| MX27_PAD_USBOTG_NXT__USBOTG_NXT 0x0 |
| MX27_PAD_USBOTG_STP__USBOTG_STP 0x0 |
| MX27_PAD_USBOTG_DATA0__USBOTG_DATA0 0x0 |
| MX27_PAD_USBOTG_DATA1__USBOTG_DATA1 0x0 |
| MX27_PAD_USBOTG_DATA2__USBOTG_DATA2 0x0 |
| MX27_PAD_USBOTG_DATA3__USBOTG_DATA3 0x0 |
| MX27_PAD_USBOTG_DATA4__USBOTG_DATA4 0x0 |
| MX27_PAD_USBOTG_DATA5__USBOTG_DATA5 0x0 |
| MX27_PAD_USBOTG_DATA6__USBOTG_DATA6 0x0 |
| MX27_PAD_USBOTG_DATA7__USBOTG_DATA7 0x0 |
| >; |
| }; |
| }; |
| }; |
