| // SPDX-License-Identifier: GPL-2.0+ |
| /* |
| * Copyright 2018-2020 NXP |
| * Dong Aisheng <aisheng.dong@nxp.com> |
| */ |
| |
| #include <dt-bindings/clock/imx8-lpcg.h> |
| #include <dt-bindings/firmware/imx/rsrc.h> |
| |
| lsio_bus_clk: clock-lsio-bus { |
| compatible = "fixed-clock"; |
| #clock-cells = <0>; |
| clock-frequency = <100000000>; |
| clock-output-names = "lsio_bus_clk"; |
| }; |
| |
| lsio_subsys: bus@5d000000 { |
| compatible = "simple-bus"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges = <0x5d000000 0x0 0x5d000000 0x1000000>, |
| <0x08000000 0x0 0x08000000 0x10000000>; |
| |
| lsio_pwm0: pwm@5d000000 { |
| compatible = "fsl,imx27-pwm"; |
| reg = <0x5d000000 0x10000>; |
| clock-names = "ipg", "per"; |
| clocks = <&pwm0_lpcg IMX_LPCG_CLK_6>, |
| <&pwm0_lpcg IMX_LPCG_CLK_1>; |
| assigned-clocks = <&clk IMX_SC_R_PWM_0 IMX_SC_PM_CLK_PER>; |
| assigned-clock-rates = <24000000>; |
| #pwm-cells = <3>; |
| interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; |
| status = "disabled"; |
| }; |
| |
| lsio_pwm1: pwm@5d010000 { |
| compatible = "fsl,imx27-pwm"; |
| reg = <0x5d010000 0x10000>; |
| clock-names = "ipg", "per"; |
| clocks = <&pwm1_lpcg IMX_LPCG_CLK_6>, |
| <&pwm1_lpcg IMX_LPCG_CLK_1>; |
| assigned-clocks = <&clk IMX_SC_R_PWM_1 IMX_SC_PM_CLK_PER>; |
| assigned-clock-rates = <24000000>; |
| #pwm-cells = <3>; |
| interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; |
| status = "disabled"; |
| }; |
| |
| lsio_pwm2: pwm@5d020000 { |
| compatible = "fsl,imx27-pwm"; |
| reg = <0x5d020000 0x10000>; |
| clock-names = "ipg", "per"; |
| clocks = <&pwm2_lpcg IMX_LPCG_CLK_6>, |
| <&pwm2_lpcg IMX_LPCG_CLK_1>; |
| assigned-clocks = <&clk IMX_SC_R_PWM_2 IMX_SC_PM_CLK_PER>; |
| assigned-clock-rates = <24000000>; |
| #pwm-cells = <3>; |
| interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; |
| status = "disabled"; |
| }; |
| |
| lsio_pwm3: pwm@5d030000 { |
| compatible = "fsl,imx27-pwm"; |
| reg = <0x5d030000 0x10000>; |
| clock-names = "ipg", "per"; |
| clocks = <&pwm3_lpcg IMX_LPCG_CLK_6>, |
| <&pwm3_lpcg IMX_LPCG_CLK_1>; |
| assigned-clocks = <&clk IMX_SC_R_PWM_3 IMX_SC_PM_CLK_PER>; |
| assigned-clock-rates = <24000000>; |
| #pwm-cells = <3>; |
| interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; |
| status = "disabled"; |
| }; |
| |
| lsio_gpio0: gpio@5d080000 { |
| reg = <0x5d080000 0x10000>; |
| interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| power-domains = <&pd IMX_SC_R_GPIO_0>; |
| }; |
| |
| lsio_gpio1: gpio@5d090000 { |
| reg = <0x5d090000 0x10000>; |
| interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| power-domains = <&pd IMX_SC_R_GPIO_1>; |
| }; |
| |
| lsio_gpio2: gpio@5d0a0000 { |
| reg = <0x5d0a0000 0x10000>; |
| interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| power-domains = <&pd IMX_SC_R_GPIO_2>; |
| }; |
| |
| lsio_gpio3: gpio@5d0b0000 { |
| reg = <0x5d0b0000 0x10000>; |
| interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| power-domains = <&pd IMX_SC_R_GPIO_3>; |
| }; |
| |
| lsio_gpio4: gpio@5d0c0000 { |
| reg = <0x5d0c0000 0x10000>; |
| interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| power-domains = <&pd IMX_SC_R_GPIO_4>; |
| }; |
| |
| lsio_gpio5: gpio@5d0d0000 { |
| reg = <0x5d0d0000 0x10000>; |
| interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| power-domains = <&pd IMX_SC_R_GPIO_5>; |
| }; |
| |
| lsio_gpio6: gpio@5d0e0000 { |
| reg = <0x5d0e0000 0x10000>; |
| interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| power-domains = <&pd IMX_SC_R_GPIO_6>; |
| }; |
| |
| lsio_gpio7: gpio@5d0f0000 { |
| reg = <0x5d0f0000 0x10000>; |
| interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| power-domains = <&pd IMX_SC_R_GPIO_7>; |
| }; |
| |
| flexspi0: spi@5d120000 { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| compatible = "nxp,imx8qxp-fspi"; |
| reg = <0x5d120000 0x10000>, <0x08000000 0x10000000>; |
| reg-names = "fspi_base", "fspi_mmap"; |
| interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&clk IMX_SC_R_FSPI_0 IMX_SC_PM_CLK_PER>, |
| <&clk IMX_SC_R_FSPI_0 IMX_SC_PM_CLK_PER>; |
| clock-names = "fspi_en", "fspi"; |
| power-domains = <&pd IMX_SC_R_FSPI_0>; |
| status = "disabled"; |
| }; |
| |
| lsio_mu0: mailbox@5d1b0000 { |
| reg = <0x5d1b0000 0x10000>; |
| interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>; |
| #mbox-cells = <2>; |
| status = "disabled"; |
| }; |
| |
| lsio_mu1: mailbox@5d1c0000 { |
| reg = <0x5d1c0000 0x10000>; |
| interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; |
| #mbox-cells = <2>; |
| }; |
| |
| lsio_mu2: mailbox@5d1d0000 { |
| reg = <0x5d1d0000 0x10000>; |
| interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>; |
| #mbox-cells = <2>; |
| status = "disabled"; |
| }; |
| |
| lsio_mu3: mailbox@5d1e0000 { |
| reg = <0x5d1e0000 0x10000>; |
| interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>; |
| #mbox-cells = <2>; |
| status = "disabled"; |
| }; |
| |
| lsio_mu4: mailbox@5d1f0000 { |
| reg = <0x5d1f0000 0x10000>; |
| interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>; |
| #mbox-cells = <2>; |
| status = "disabled"; |
| }; |
| |
| lsio_mu5: mailbox@5d200000 { |
| reg = <0x5d200000 0x10000>; |
| interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; |
| #mbox-cells = <2>; |
| power-domains = <&pd IMX_SC_R_MU_5A>; |
| status = "disabled"; |
| }; |
| |
| lsio_mu6: mailbox@5d210000 { |
| reg = <0x5d210000 0x10000>; |
| interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>; |
| #mbox-cells = <2>; |
| power-domains = <&pd IMX_SC_R_MU_6A>; |
| status = "disabled"; |
| }; |
| |
| lsio_mu13: mailbox@5d280000 { |
| reg = <0x5d280000 0x10000>; |
| interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>; |
| #mbox-cells = <2>; |
| power-domains = <&pd IMX_SC_R_MU_13A>; |
| }; |
| |
| /* LPCG clocks */ |
| pwm0_lpcg: clock-controller@5d400000 { |
| compatible = "fsl,imx8qxp-lpcg"; |
| reg = <0x5d400000 0x10000>; |
| #clock-cells = <1>; |
| clocks = <&clk IMX_SC_R_PWM_0 IMX_SC_PM_CLK_PER>, |
| <&clk IMX_SC_R_PWM_0 IMX_SC_PM_CLK_PER>, |
| <&clk IMX_SC_R_PWM_0 IMX_SC_PM_CLK_PER>, |
| <&lsio_bus_clk>, |
| <&clk IMX_SC_R_PWM_0 IMX_SC_PM_CLK_PER>; |
| clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>, |
| <IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>, |
| <IMX_LPCG_CLK_6>; |
| clock-output-names = "pwm0_lpcg_ipg_clk", |
| "pwm0_lpcg_ipg_hf_clk", |
| "pwm0_lpcg_ipg_s_clk", |
| "pwm0_lpcg_ipg_slv_clk", |
| "pwm0_lpcg_ipg_mstr_clk"; |
| power-domains = <&pd IMX_SC_R_PWM_0>; |
| }; |
| |
| pwm1_lpcg: clock-controller@5d410000 { |
| compatible = "fsl,imx8qxp-lpcg"; |
| reg = <0x5d410000 0x10000>; |
| #clock-cells = <1>; |
| clocks = <&clk IMX_SC_R_PWM_1 IMX_SC_PM_CLK_PER>, |
| <&clk IMX_SC_R_PWM_1 IMX_SC_PM_CLK_PER>, |
| <&clk IMX_SC_R_PWM_1 IMX_SC_PM_CLK_PER>, |
| <&lsio_bus_clk>, |
| <&clk IMX_SC_R_PWM_1 IMX_SC_PM_CLK_PER>; |
| clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>, |
| <IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>, |
| <IMX_LPCG_CLK_6>; |
| clock-output-names = "pwm1_lpcg_ipg_clk", |
| "pwm1_lpcg_ipg_hf_clk", |
| "pwm1_lpcg_ipg_s_clk", |
| "pwm1_lpcg_ipg_slv_clk", |
| "pwm1_lpcg_ipg_mstr_clk"; |
| power-domains = <&pd IMX_SC_R_PWM_1>; |
| }; |
| |
| pwm2_lpcg: clock-controller@5d420000 { |
| compatible = "fsl,imx8qxp-lpcg"; |
| reg = <0x5d420000 0x10000>; |
| #clock-cells = <1>; |
| clocks = <&clk IMX_SC_R_PWM_2 IMX_SC_PM_CLK_PER>, |
| <&clk IMX_SC_R_PWM_2 IMX_SC_PM_CLK_PER>, |
| <&clk IMX_SC_R_PWM_2 IMX_SC_PM_CLK_PER>, |
| <&lsio_bus_clk>, |
| <&clk IMX_SC_R_PWM_2 IMX_SC_PM_CLK_PER>; |
| clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>, |
| <IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>, |
| <IMX_LPCG_CLK_6>; |
| clock-output-names = "pwm2_lpcg_ipg_clk", |
| "pwm2_lpcg_ipg_hf_clk", |
| "pwm2_lpcg_ipg_s_clk", |
| "pwm2_lpcg_ipg_slv_clk", |
| "pwm2_lpcg_ipg_mstr_clk"; |
| power-domains = <&pd IMX_SC_R_PWM_2>; |
| }; |
| |
| pwm3_lpcg: clock-controller@5d430000 { |
| compatible = "fsl,imx8qxp-lpcg"; |
| reg = <0x5d430000 0x10000>; |
| #clock-cells = <1>; |
| clocks = <&clk IMX_SC_R_PWM_3 IMX_SC_PM_CLK_PER>, |
| <&clk IMX_SC_R_PWM_3 IMX_SC_PM_CLK_PER>, |
| <&clk IMX_SC_R_PWM_3 IMX_SC_PM_CLK_PER>, |
| <&lsio_bus_clk>, |
| <&clk IMX_SC_R_PWM_3 IMX_SC_PM_CLK_PER>; |
| clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>, |
| <IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>, |
| <IMX_LPCG_CLK_6>; |
| clock-output-names = "pwm3_lpcg_ipg_clk", |
| "pwm3_lpcg_ipg_hf_clk", |
| "pwm3_lpcg_ipg_s_clk", |
| "pwm3_lpcg_ipg_slv_clk", |
| "pwm3_lpcg_ipg_mstr_clk"; |
| power-domains = <&pd IMX_SC_R_PWM_3>; |
| }; |
| |
| pwm4_lpcg: clock-controller@5d440000 { |
| compatible = "fsl,imx8qxp-lpcg"; |
| reg = <0x5d440000 0x10000>; |
| #clock-cells = <1>; |
| clocks = <&clk IMX_SC_R_PWM_4 IMX_SC_PM_CLK_PER>, |
| <&clk IMX_SC_R_PWM_4 IMX_SC_PM_CLK_PER>, |
| <&clk IMX_SC_R_PWM_4 IMX_SC_PM_CLK_PER>, |
| <&lsio_bus_clk>, |
| <&clk IMX_SC_R_PWM_4 IMX_SC_PM_CLK_PER>; |
| clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>, |
| <IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>, |
| <IMX_LPCG_CLK_6>; |
| clock-output-names = "pwm4_lpcg_ipg_clk", |
| "pwm4_lpcg_ipg_hf_clk", |
| "pwm4_lpcg_ipg_s_clk", |
| "pwm4_lpcg_ipg_slv_clk", |
| "pwm4_lpcg_ipg_mstr_clk"; |
| power-domains = <&pd IMX_SC_R_PWM_4>; |
| }; |
| |
| pwm5_lpcg: clock-controller@5d450000 { |
| compatible = "fsl,imx8qxp-lpcg"; |
| reg = <0x5d450000 0x10000>; |
| #clock-cells = <1>; |
| clocks = <&clk IMX_SC_R_PWM_5 IMX_SC_PM_CLK_PER>, |
| <&clk IMX_SC_R_PWM_5 IMX_SC_PM_CLK_PER>, |
| <&clk IMX_SC_R_PWM_5 IMX_SC_PM_CLK_PER>, |
| <&lsio_bus_clk>, |
| <&clk IMX_SC_R_PWM_5 IMX_SC_PM_CLK_PER>; |
| clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>, |
| <IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>, |
| <IMX_LPCG_CLK_6>; |
| clock-output-names = "pwm5_lpcg_ipg_clk", |
| "pwm5_lpcg_ipg_hf_clk", |
| "pwm5_lpcg_ipg_s_clk", |
| "pwm5_lpcg_ipg_slv_clk", |
| "pwm5_lpcg_ipg_mstr_clk"; |
| power-domains = <&pd IMX_SC_R_PWM_5>; |
| }; |
| |
| pwm6_lpcg: clock-controller@5d460000 { |
| compatible = "fsl,imx8qxp-lpcg"; |
| reg = <0x5d460000 0x10000>; |
| #clock-cells = <1>; |
| clocks = <&clk IMX_SC_R_PWM_6 IMX_SC_PM_CLK_PER>, |
| <&clk IMX_SC_R_PWM_6 IMX_SC_PM_CLK_PER>, |
| <&clk IMX_SC_R_PWM_6 IMX_SC_PM_CLK_PER>, |
| <&lsio_bus_clk>, |
| <&clk IMX_SC_R_PWM_6 IMX_SC_PM_CLK_PER>; |
| clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>, |
| <IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>, |
| <IMX_LPCG_CLK_6>; |
| clock-output-names = "pwm6_lpcg_ipg_clk", |
| "pwm6_lpcg_ipg_hf_clk", |
| "pwm6_lpcg_ipg_s_clk", |
| "pwm6_lpcg_ipg_slv_clk", |
| "pwm6_lpcg_ipg_mstr_clk"; |
| power-domains = <&pd IMX_SC_R_PWM_6>; |
| }; |
| |
| pwm7_lpcg: clock-controller@5d470000 { |
| compatible = "fsl,imx8qxp-lpcg"; |
| reg = <0x5d470000 0x10000>; |
| #clock-cells = <1>; |
| clocks = <&clk IMX_SC_R_PWM_7 IMX_SC_PM_CLK_PER>, |
| <&clk IMX_SC_R_PWM_7 IMX_SC_PM_CLK_PER>, |
| <&clk IMX_SC_R_PWM_7 IMX_SC_PM_CLK_PER>, |
| <&lsio_bus_clk>, |
| <&clk IMX_SC_R_PWM_7 IMX_SC_PM_CLK_PER>; |
| clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>, |
| <IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>, |
| <IMX_LPCG_CLK_6>; |
| clock-output-names = "pwm7_lpcg_ipg_clk", |
| "pwm7_lpcg_ipg_hf_clk", |
| "pwm7_lpcg_ipg_s_clk", |
| "pwm7_lpcg_ipg_slv_clk", |
| "pwm7_lpcg_ipg_mstr_clk"; |
| power-domains = <&pd IMX_SC_R_PWM_7>; |
| }; |
| }; |
