| /* SPDX-License-Identifier: GPL-2.0 */ |
| /* |
| * Copyright (c) 2024 Qualcomm Innovation Center. All rights reserved. |
| */ |
| |
| #ifndef QCOM_PHY_QMP_PCS_PCIE_V6_30_H_ |
| #define QCOM_PHY_QMP_PCS_PCIE_V6_30_H_ |
| |
| /* Only for QMP V6_30 PHY - PCIE have different offsets than V6 */ |
| #define QPHY_PCIE_V6_30_PCS_POWER_STATE_CONFIG2 0x014 |
| #define QPHY_PCIE_V6_30_PCS_TX_RX_CONFIG 0x020 |
| #define QPHY_PCIE_V6_30_PCS_ENDPOINT_REFCLK_DRIVE 0x024 |
| #define QPHY_PCIE_V6_30_PCS_OSC_DTCT_ACTIONS 0x098 |
| #define QPHY_PCIE_V6_30_PCS_EQ_CONFIG1 0x0a8 |
| #define QPHY_PCIE_V6_30_PCS_G3_RXEQEVAL_TIME 0x0f8 |
| #define QPHY_PCIE_V6_30_PCS_G4_RXEQEVAL_TIME 0x0fc |
| #define QPHY_PCIE_V6_30_PCS_G4_EQ_CONFIG5 0x110 |
| #define QPHY_PCIE_V6_30_PCS_G4_PRE_GAIN 0x164 |
| #define QPHY_PCIE_V6_30_PCS_RX_MARGINING_CONFIG1 0x184 |
| #define QPHY_PCIE_V6_30_PCS_RX_MARGINING_CONFIG3 0x18c |
| #define QPHY_PCIE_V6_30_PCS_RX_MARGINING_CONFIG5 0x194 |
| #define QPHY_PCIE_V6_30_PCS_G3_FOM_EQ_CONFIG5 0x1b4 |
| #define QPHY_PCIE_V6_30_PCS_G4_FOM_EQ_CONFIG5 0x1c8 |
| |
| #endif |
