| /* SPDX-License-Identifier: GPL-2.0 */ | |
| /* | |
| * MIO pin configuration defines for Xilinx Zynq | |
| * | |
| * Copyright (C) 2021 Xilinx, Inc. | |
| */ | |
| #ifndef _DT_BINDINGS_PINCTRL_ZYNQ_H | |
| #define _DT_BINDINGS_PINCTRL_ZYNQ_H | |
| /* Configuration options for different power supplies */ | |
| #define IO_STANDARD_LVCMOS18 1 | |
| #define IO_STANDARD_LVCMOS25 2 | |
| #define IO_STANDARD_LVCMOS33 3 | |
| #define IO_STANDARD_HSTL 4 | |
| #endif /* _DT_BINDINGS_PINCTRL_ZYNQ_H */ |