| // SPDX-License-Identifier: GPL-2.0+ OR MIT |
| /* |
| * Apple T8015 "A11" SoC |
| * |
| * Other names: H10, "Skye" |
| * |
| * Copyright (c) 2022, Konrad Dybcio <konradybcio@kernel.org> |
| */ |
| |
| #include <dt-bindings/gpio/gpio.h> |
| #include <dt-bindings/interrupt-controller/apple-aic.h> |
| #include <dt-bindings/interrupt-controller/irq.h> |
| #include <dt-bindings/pinctrl/apple.h> |
| |
| / { |
| interrupt-parent = <&aic>; |
| #address-cells = <2>; |
| #size-cells = <2>; |
| |
| clkref: clock-ref { |
| compatible = "fixed-clock"; |
| #clock-cells = <0>; |
| clock-frequency = <24000000>; |
| clock-output-names = "clkref"; |
| }; |
| |
| cpus { |
| #address-cells = <2>; |
| #size-cells = <0>; |
| |
| cpu-map { |
| cluster0 { |
| core0 { |
| cpu = <&cpu_e0>; |
| }; |
| core1 { |
| cpu = <&cpu_e1>; |
| }; |
| core2 { |
| cpu = <&cpu_e2>; |
| }; |
| core3 { |
| cpu = <&cpu_e3>; |
| }; |
| }; |
| |
| cluster1 { |
| core0 { |
| cpu = <&cpu_p0>; |
| }; |
| core1 { |
| cpu = <&cpu_p1>; |
| }; |
| }; |
| }; |
| |
| cpu_e0: cpu@0 { |
| compatible = "apple,mistral"; |
| reg = <0x0 0x0>; |
| cpu-release-addr = <0 0>; /* To be filled by loader */ |
| performance-domains = <&cpufreq_e>; |
| operating-points-v2 = <&mistral_opp>; |
| capacity-dmips-mhz = <633>; |
| enable-method = "spin-table"; |
| device_type = "cpu"; |
| next-level-cache = <&l2_cache_0>; |
| i-cache-size = <0x8000>; |
| d-cache-size = <0x8000>; |
| }; |
| |
| cpu_e1: cpu@1 { |
| compatible = "apple,mistral"; |
| reg = <0x0 0x1>; |
| cpu-release-addr = <0 0>; /* To be filled by loader */ |
| performance-domains = <&cpufreq_e>; |
| operating-points-v2 = <&mistral_opp>; |
| capacity-dmips-mhz = <633>; |
| enable-method = "spin-table"; |
| device_type = "cpu"; |
| next-level-cache = <&l2_cache_0>; |
| i-cache-size = <0x8000>; |
| d-cache-size = <0x8000>; |
| }; |
| |
| cpu_e2: cpu@2 { |
| compatible = "apple,mistral"; |
| reg = <0x0 0x2>; |
| cpu-release-addr = <0 0>; /* To be filled by loader */ |
| performance-domains = <&cpufreq_e>; |
| operating-points-v2 = <&mistral_opp>; |
| capacity-dmips-mhz = <633>; |
| enable-method = "spin-table"; |
| device_type = "cpu"; |
| next-level-cache = <&l2_cache_0>; |
| i-cache-size = <0x8000>; |
| d-cache-size = <0x8000>; |
| }; |
| |
| cpu_e3: cpu@3 { |
| compatible = "apple,mistral"; |
| reg = <0x0 0x3>; |
| cpu-release-addr = <0 0>; /* To be filled by loader */ |
| performance-domains = <&cpufreq_e>; |
| operating-points-v2 = <&mistral_opp>; |
| capacity-dmips-mhz = <633>; |
| enable-method = "spin-table"; |
| device_type = "cpu"; |
| next-level-cache = <&l2_cache_0>; |
| i-cache-size = <0x8000>; |
| d-cache-size = <0x8000>; |
| }; |
| |
| cpu_p0: cpu@10004 { |
| compatible = "apple,monsoon"; |
| reg = <0x0 0x10004>; |
| cpu-release-addr = <0 0>; /* To be filled by loader */ |
| performance-domains = <&cpufreq_p>; |
| operating-points-v2 = <&monsoon_opp>; |
| capacity-dmips-mhz = <1024>; |
| enable-method = "spin-table"; |
| device_type = "cpu"; |
| next-level-cache = <&l2_cache_1>; |
| i-cache-size = <0x10000>; |
| d-cache-size = <0x10000>; |
| }; |
| |
| cpu_p1: cpu@10005 { |
| compatible = "apple,monsoon"; |
| reg = <0x0 0x10005>; |
| cpu-release-addr = <0 0>; /* To be filled by loader */ |
| performance-domains = <&cpufreq_p>; |
| operating-points-v2 = <&monsoon_opp>; |
| capacity-dmips-mhz = <1024>; |
| enable-method = "spin-table"; |
| device_type = "cpu"; |
| next-level-cache = <&l2_cache_1>; |
| i-cache-size = <0x10000>; |
| d-cache-size = <0x10000>; |
| }; |
| |
| l2_cache_0: l2-cache-0 { |
| compatible = "cache"; |
| cache-level = <2>; |
| cache-unified; |
| cache-size = <0x100000>; |
| }; |
| |
| l2_cache_1: l2-cache-1 { |
| compatible = "cache"; |
| cache-level = <2>; |
| cache-unified; |
| cache-size = <0x800000>; |
| }; |
| }; |
| |
| mistral_opp: opp-table-0 { |
| compatible = "operating-points-v2"; |
| |
| opp01 { |
| opp-hz = /bits/ 64 <300000000>; |
| opp-level = <1>; |
| clock-latency-ns = <1800>; |
| }; |
| opp02 { |
| opp-hz = /bits/ 64 <453000000>; |
| opp-level = <2>; |
| clock-latency-ns = <140000>; |
| }; |
| opp03 { |
| opp-hz = /bits/ 64 <672000000>; |
| opp-level = <3>; |
| clock-latency-ns = <105000>; |
| }; |
| opp04 { |
| opp-hz = /bits/ 64 <972000000>; |
| opp-level = <4>; |
| clock-latency-ns = <115000>; |
| }; |
| opp05 { |
| opp-hz = /bits/ 64 <1272000000>; |
| opp-level = <5>; |
| clock-latency-ns = <125000>; |
| }; |
| opp06 { |
| opp-hz = /bits/ 64 <1572000000>; |
| opp-level = <6>; |
| clock-latency-ns = <135000>; |
| }; |
| #if 0 |
| /* Not available until CPU deep sleep is implemented */ |
| opp07 { |
| opp-hz = /bits/ 64 <1680000000>; |
| opp-level = <7>; |
| clock-latency-ns = <135000>; |
| turbo-mode; |
| }; |
| #endif |
| }; |
| |
| monsoon_opp: opp-table-1 { |
| compatible = "operating-points-v2"; |
| |
| opp01 { |
| opp-hz = /bits/ 64 <300000000>; |
| opp-level = <1>; |
| clock-latency-ns = <1400>; |
| }; |
| opp02 { |
| opp-hz = /bits/ 64 <453000000>; |
| opp-level = <2>; |
| clock-latency-ns = <140000>; |
| }; |
| opp03 { |
| opp-hz = /bits/ 64 <853000000>; |
| opp-level = <3>; |
| clock-latency-ns = <110000>; |
| }; |
| opp04 { |
| opp-hz = /bits/ 64 <1332000000>; |
| opp-level = <4>; |
| clock-latency-ns = <110000>; |
| }; |
| opp05 { |
| opp-hz = /bits/ 64 <1812000000>; |
| opp-level = <5>; |
| clock-latency-ns = <125000>; |
| }; |
| opp06 { |
| opp-hz = /bits/ 64 <2064000000>; |
| opp-level = <6>; |
| clock-latency-ns = <130000>; |
| }; |
| opp07 { |
| opp-hz = /bits/ 64 <2304000000>; |
| opp-level = <7>; |
| clock-latency-ns = <140000>; |
| }; |
| #if 0 |
| /* Not available until CPU deep sleep is implemented */ |
| opp08 { |
| opp-hz = /bits/ 64 <2376000000>; |
| opp-level = <8>; |
| clock-latency-ns = <140000>; |
| turbo-mode; |
| }; |
| #endif |
| }; |
| |
| soc { |
| compatible = "simple-bus"; |
| #address-cells = <2>; |
| #size-cells = <2>; |
| nonposted-mmio; |
| ranges; |
| |
| cpufreq_e: performance-controller@208e20000 { |
| compatible = "apple,t8015-cluster-cpufreq", "apple,t8103-cluster-cpufreq", "apple,cluster-cpufreq"; |
| reg = <0x2 0x08e20000 0 0x1000>; |
| #performance-domain-cells = <0>; |
| }; |
| |
| cpufreq_p: performance-controller@208ea0000 { |
| compatible = "apple,t8015-cluster-cpufreq", "apple,t8103-cluster-cpufreq", "apple,cluster-cpufreq"; |
| reg = <0x2 0x08ea0000 0 0x1000>; |
| #performance-domain-cells = <0>; |
| }; |
| |
| serial0: serial@22e600000 { |
| compatible = "apple,s5l-uart"; |
| reg = <0x2 0x2e600000 0x0 0x4000>; |
| reg-io-width = <4>; |
| interrupt-parent = <&aic>; |
| interrupts = <AIC_IRQ 282 IRQ_TYPE_LEVEL_HIGH>; |
| /* Use the bootloader-enabled clocks for now. */ |
| clocks = <&clkref>, <&clkref>; |
| clock-names = "uart", "clk_uart_baud0"; |
| power-domains = <&ps_uart0>; |
| status = "disabled"; |
| }; |
| |
| aic: interrupt-controller@232100000 { |
| compatible = "apple,t8015-aic", "apple,aic"; |
| reg = <0x2 0x32100000 0x0 0x8000>; |
| #interrupt-cells = <3>; |
| interrupt-controller; |
| power-domains = <&ps_aic>; |
| }; |
| |
| pmgr: power-management@232000000 { |
| compatible = "apple,t8015-pmgr", "apple,pmgr", "syscon", "simple-mfd"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| |
| reg = <0x2 0x32000000 0 0x8c000>; |
| }; |
| |
| dwi_bl: backlight@232200080 { |
| compatible = "apple,t8015-dwi-bl", "apple,dwi-bl"; |
| reg = <0x2 0x32200080 0x0 0x8>; |
| power-domains = <&ps_dwi>; |
| status = "disabled"; |
| }; |
| |
| pinctrl_ap: pinctrl@233100000 { |
| compatible = "apple,t8015-pinctrl", "apple,pinctrl"; |
| reg = <0x2 0x33100000 0x0 0x1000>; |
| power-domains = <&ps_gpio>; |
| |
| gpio-controller; |
| #gpio-cells = <2>; |
| gpio-ranges = <&pinctrl_ap 0 0 223>; |
| apple,npins = <223>; |
| |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| interrupt-parent = <&aic>; |
| interrupts = <AIC_IRQ 50 IRQ_TYPE_LEVEL_HIGH>, |
| <AIC_IRQ 51 IRQ_TYPE_LEVEL_HIGH>, |
| <AIC_IRQ 52 IRQ_TYPE_LEVEL_HIGH>, |
| <AIC_IRQ 53 IRQ_TYPE_LEVEL_HIGH>, |
| <AIC_IRQ 54 IRQ_TYPE_LEVEL_HIGH>, |
| <AIC_IRQ 55 IRQ_TYPE_LEVEL_HIGH>, |
| <AIC_IRQ 56 IRQ_TYPE_LEVEL_HIGH>; |
| }; |
| |
| pinctrl_aop: pinctrl@2340f0000 { |
| compatible = "apple,t8015-pinctrl", "apple,pinctrl"; |
| reg = <0x2 0x340f0000 0x0 0x4000>; |
| |
| gpio-controller; |
| #gpio-cells = <2>; |
| gpio-ranges = <&pinctrl_aop 0 0 49>; |
| apple,npins = <49>; |
| |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| interrupt-parent = <&aic>; |
| interrupts = <AIC_IRQ 135 IRQ_TYPE_LEVEL_HIGH>, |
| <AIC_IRQ 136 IRQ_TYPE_LEVEL_HIGH>, |
| <AIC_IRQ 137 IRQ_TYPE_LEVEL_HIGH>, |
| <AIC_IRQ 138 IRQ_TYPE_LEVEL_HIGH>, |
| <AIC_IRQ 139 IRQ_TYPE_LEVEL_HIGH>, |
| <AIC_IRQ 140 IRQ_TYPE_LEVEL_HIGH>, |
| <AIC_IRQ 141 IRQ_TYPE_LEVEL_HIGH>; |
| }; |
| |
| pinctrl_nub: pinctrl@2351f0000 { |
| compatible = "apple,t8015-pinctrl", "apple,pinctrl"; |
| reg = <0x2 0x351f0000 0x0 0x4000>; |
| |
| gpio-controller; |
| #gpio-cells = <2>; |
| gpio-ranges = <&pinctrl_nub 0 0 8>; |
| apple,npins = <8>; |
| |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| interrupt-parent = <&aic>; |
| interrupts = <AIC_IRQ 168 IRQ_TYPE_LEVEL_HIGH>, |
| <AIC_IRQ 169 IRQ_TYPE_LEVEL_HIGH>, |
| <AIC_IRQ 170 IRQ_TYPE_LEVEL_HIGH>; |
| }; |
| |
| pmgr_mini: power-management@235200000 { |
| compatible = "apple,t8015-pmgr", "apple,pmgr", "syscon", "simple-mfd"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| |
| reg = <0x2 0x35200000 0 0x84000>; |
| }; |
| |
| wdt: watchdog@2352b0000 { |
| compatible = "apple,t8015-wdt", "apple,wdt"; |
| reg = <0x2 0x352b0000 0x0 0x4000>; |
| clocks = <&clkref>; |
| interrupt-parent = <&aic>; |
| interrupts = <AIC_IRQ 172 IRQ_TYPE_LEVEL_HIGH>; |
| }; |
| |
| pinctrl_smc: pinctrl@236024000 { |
| compatible = "apple,t8015-pinctrl", "apple,pinctrl"; |
| reg = <0x2 0x36024000 0x0 0x4000>; |
| |
| gpio-controller; |
| #gpio-cells = <2>; |
| gpio-ranges = <&pinctrl_smc 0 0 6>; |
| apple,npins = <6>; |
| |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| interrupt-parent = <&aic>; |
| interrupts = <AIC_IRQ 199 IRQ_TYPE_LEVEL_HIGH>, |
| <AIC_IRQ 200 IRQ_TYPE_LEVEL_HIGH>, |
| <AIC_IRQ 201 IRQ_TYPE_LEVEL_HIGH>, |
| <AIC_IRQ 202 IRQ_TYPE_LEVEL_HIGH>, |
| <AIC_IRQ 203 IRQ_TYPE_LEVEL_HIGH>, |
| <AIC_IRQ 204 IRQ_TYPE_LEVEL_HIGH>, |
| <AIC_IRQ 205 IRQ_TYPE_LEVEL_HIGH>; |
| /* |
| * SMC is not yet supported and accessing this pinctrl while SMC is |
| * suspended results in a hang. |
| */ |
| status = "disabled"; |
| }; |
| }; |
| |
| timer { |
| compatible = "arm,armv8-timer"; |
| interrupt-parent = <&aic>; |
| interrupt-names = "phys", "virt"; |
| /* Note that A11 doesn't actually have a hypervisor (EL2 is not implemented). */ |
| interrupts = <AIC_FIQ AIC_TMR_GUEST_PHYS IRQ_TYPE_LEVEL_HIGH>, |
| <AIC_FIQ AIC_TMR_GUEST_VIRT IRQ_TYPE_LEVEL_HIGH>; |
| }; |
| }; |
| |
| #include "t8015-pmgr.dtsi" |
