| // SPDX-License-Identifier: (GPL-2.0 OR MIT) |
| /* |
| * Copyright (C) 2021 Lothar Waßmann <LW@KARO-electronics.de> |
| * 2025 Maud Spierings <maudspierings@gocontroll.com> |
| */ |
| |
| #include "imx8mm.dtsi" |
| |
| / { |
| model = "Ka-Ro Electronics TX8M-1610"; |
| compatible = "karo,tx8m-1610", "fsl,imx8mm"; |
| |
| reg_3v3_etn: regulator-3v3-etn { |
| compatible = "regulator-fixed"; |
| enable-active-high; |
| gpio = <&gpio1 23 GPIO_ACTIVE_HIGH>; |
| pinctrl-0 = <&pinctrl_reg_3v3_etn>; |
| pinctrl-names = "default"; |
| regulator-boot-on; |
| regulator-max-microvolt = <3300000>; |
| regulator-min-microvolt = <3300000>; |
| regulator-name = "3v3-etn"; |
| }; |
| }; |
| |
| &A53_0 { |
| cpu-supply = <®_vdd_arm>; |
| }; |
| |
| &A53_1 { |
| cpu-supply = <®_vdd_arm>; |
| }; |
| |
| &A53_2 { |
| cpu-supply = <®_vdd_arm>; |
| }; |
| |
| &A53_3 { |
| cpu-supply = <®_vdd_arm>; |
| }; |
| |
| &ddrc { |
| operating-points-v2 = <&ddrc_opp_table>; |
| |
| ddrc_opp_table: opp-table { |
| compatible = "operating-points-v2"; |
| |
| opp-400000000 { |
| opp-hz = /bits/ 64 <400000000>; |
| }; |
| }; |
| }; |
| |
| &fec1 { |
| assigned-clocks = <&clk IMX8MM_CLK_ENET_AXI>, |
| <&clk IMX8MM_CLK_ENET_TIMER>, |
| <&clk IMX8MM_CLK_ENET_REF>, |
| <&clk IMX8MM_CLK_ENET_REF>; |
| assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_266M>, |
| <&clk IMX8MM_SYS_PLL2_100M>, |
| <&clk IMX8MM_SYS_PLL2_50M>, |
| <&clk IMX8MM_SYS_PLL2_50M>; |
| assigned-clock-rates = <0>, <100000000>, <50000000>, <50000000>; |
| clocks = <&clk IMX8MM_CLK_ENET1_ROOT>, |
| <&clk IMX8MM_CLK_ENET1_ROOT>, |
| <&clk IMX8MM_CLK_ENET_TIMER>, |
| <&clk IMX8MM_CLK_ENET_REF>; |
| phy-handle = <ðphy0>; |
| phy-mode = "rmii"; |
| phy-reset-duration = <25>; |
| phy-reset-gpios = <&gpio1 29 GPIO_ACTIVE_LOW>; |
| phy-reset-post-delay = <1>; |
| phy-supply = <®_3v3_etn>; |
| pinctrl-0 = <&pinctrl_fec1>, <&pinctrl_ethphy_rst>; |
| pinctrl-names = "default"; |
| status = "okay"; |
| |
| mdio { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| ethphy0: ethernet-phy@0 { |
| reg = <0>; |
| clocks = <&clk IMX8MM_CLK_ENET_REF>; |
| interrupt-parent = <&gpio1>; |
| interrupts = <28 IRQ_TYPE_EDGE_FALLING>; |
| pinctrl-0 = <&pinctrl_ethphy_int>; |
| pinctrl-names = "default"; |
| smsc,disable-energy-detect; |
| }; |
| }; |
| }; |
| |
| &gpio1 { |
| gpio-line-names = "SODIMM_152", "SODIMM_42", "SODIMM_153", "PMIC_IRQ_B", |
| "SODIMM_154", "SODIMM_155", "SODIMM_156", "SODIMM_157", |
| "SODIMM_158", "SODIMM_159", "SODIMM_161", "SODIMM_162", |
| "SODIMM_34", "SODIMM_36", "SODIMM_27", "SODIMM_28", |
| "", "", "", "", |
| "", "", "", "ENET_POWER", |
| "", "", "", "", |
| "ENET_nINT", "ENET_nRST", "", ""; |
| }; |
| |
| &gpio2 { |
| gpio-line-names = "", "", "", "", |
| "", "", "", "", |
| "", "", "", "", |
| "SODIMM_51", "SODIMM_57", "SODIMM_56", "SODIMM_52", |
| "SODIMM_53", "SODIMM_54", "SODIMM_55", "SODIMM_15", |
| "SODIMM_45", "", "", "", |
| "", "", "", "", |
| "", "", "", ""; |
| }; |
| |
| &gpio3 { |
| gpio-line-names = "SODIMM_103", "SODIMM_104", "SODIMM_105", "SODIMM_106", |
| "SODIMM_107", "SODIMM_112", "SODIMM_108", "SODIMM_109", |
| "SODIMM_95", "SODIMM_110", "SODIMM_96", "SODIMM_97", |
| "SODIMM_98", "SODIMM_99", "SODIMM_113", "SODIMM_114", |
| "SODIMM_115", "SODIMM_101", "SODIMM_100", "SODIMM_77", |
| "SODIMM_72", "SODIMM_73", "SODIMM_74", "SODIMM_75", |
| "SODIMM_76", "SODIMM_43", "", "", |
| "", "", "", ""; |
| }; |
| |
| &gpio4 { |
| gpio-line-names = "SODIMM_178", "SODIMM_180", "SODIMM_184", "SODIMM_185", |
| "SODIMM_186", "SODIMM_187", "SODIMM_188", "SODIMM_189", |
| "SODIMM_190", "SODIMM_191", "SODIMM_179", "SODIMM_181", |
| "SODIMM_192", "SODIMM_193", "SODIMM_194", "SODIMM_195", |
| "SODIMM_196", "SODIMM_197", "SODIMM_198", "SODIMM_199", |
| "SODIMM_182", "SODIMM_79", "SODIMM_78", "SODIMM_84", |
| "SODIMM_87", "SODIMM_86", "SODIMM_85", "SODIMM_83", |
| "SODIMM_81", "SODIMM_80", "SODIMM_90", "SODIMM_93"; |
| }; |
| |
| &gpio5 { |
| gpio-line-names = "SODIMM_92", "SODIMM_91", "SODIMM_89", "SODIMM_144", |
| "SODIMM_143", "SODIMM_146", "SODIMM_68", "SODIMM_67", |
| "SODIMM_70", "SODIMM_69", "SODIMM_48", "SODIMM_46", |
| "SODIMM_47", "SODIMM_44", "PMIC_SCL", "PMIC_SDA", |
| "SODIMM_41", "SODIMM_40", "SODIMM_148", "SODIMM_149", |
| "SODIMM_150", "SODIMM_151", "SODIMM_60", "SODIMM_59", |
| "SODIMM_64", "SODIMM_63", "SODIMM_62", "SODIMM_61", |
| "SODIMM_66", "SODIMM_65", "", ""; |
| }; |
| |
| &i2c1 { |
| clock-frequency = <400000>; |
| pinctrl-0 = <&pinctrl_i2c1>; |
| pinctrl-1 = <&pinctrl_i2c1_gpio>; |
| pinctrl-names = "default", "gpio"; |
| scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; |
| sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; |
| status = "okay"; |
| |
| pmic: pmic@4b { |
| compatible = "rohm,bd71847"; |
| reg = <0x4b>; |
| interrupt-parent = <&gpio1>; |
| interrupts = <3 IRQ_TYPE_LEVEL_LOW>; |
| pinctrl-0 = <&pinctrl_pmic>; |
| pinctrl-names = "default"; |
| rohm,reset-snvs-powered; |
| |
| regulators { |
| BUCK1 { |
| regulator-always-on; |
| regulator-boot-on; |
| regulator-max-microvolt = <900000>; |
| regulator-min-microvolt = <780000>; |
| regulator-name = "buck1"; |
| regulator-ramp-delay = <1250>; |
| }; |
| |
| reg_vdd_arm: BUCK2 { |
| regulator-always-on; |
| regulator-boot-on; |
| regulator-max-microvolt = <950000>; |
| regulator-min-microvolt = <805000>; |
| regulator-name = "buck2"; |
| regulator-ramp-delay = <1250>; |
| rohm,dvs-run-voltage = <950000>; |
| rohm,dvs-idle-voltage = <810000>; |
| }; |
| |
| BUCK3 { |
| regulator-always-on; |
| regulator-boot-on; |
| regulator-max-microvolt = <900000>; |
| regulator-min-microvolt = <805000>; |
| regulator-name = "buck3"; |
| }; |
| |
| reg_vdd_3v3: BUCK4 { |
| regulator-always-on; |
| regulator-boot-on; |
| regulator-max-microvolt = <3300000>; |
| regulator-min-microvolt = <3300000>; |
| regulator-name = "buck4"; |
| }; |
| |
| reg_vdd_1v8: BUCK5 { |
| regulator-always-on; |
| regulator-boot-on; |
| regulator-max-microvolt = <1950000>; |
| regulator-min-microvolt = <1700000>; |
| regulator-name = "buck5"; |
| }; |
| |
| BUCK6 { |
| regulator-always-on; |
| regulator-boot-on; |
| regulator-max-microvolt = <(1350000 + 100000)>; |
| regulator-min-microvolt = <(1350000 - 67000)>; |
| regulator-name = "buck6"; |
| rohm,fb-pull-up-microvolt = <0>; |
| rohm,feedback-pull-up-r1-ohms = <2200>; |
| rohm,feedback-pull-up-r2-ohms = <499>; |
| }; |
| |
| LDO1 { |
| regulator-always-on; |
| regulator-boot-on; |
| regulator-max-microvolt = <1980000>; |
| regulator-min-microvolt = <1620000>; |
| regulator-name = "ldo1"; |
| }; |
| |
| LDO2 { |
| regulator-always-on; |
| regulator-boot-on; |
| regulator-max-microvolt = <900000>; |
| regulator-min-microvolt = <760000>; |
| regulator-name = "ldo2"; |
| }; |
| |
| LDO3 { |
| regulator-always-on; |
| regulator-boot-on; |
| regulator-max-microvolt = <1890000>; |
| regulator-min-microvolt = <1710000>; |
| regulator-name = "ldo3"; |
| }; |
| |
| LDO4 { |
| regulator-always-on; |
| regulator-boot-on; |
| regulator-max-microvolt = <1000000>; |
| regulator-min-microvolt = <855000>; |
| regulator-name = "ldo4"; |
| }; |
| |
| LDO5 { |
| regulator-max-microvolt = <3300000>; |
| regulator-min-microvolt = <1800000>; |
| regulator-name = "ldo5"; |
| }; |
| |
| LDO6 { |
| regulator-always-on; |
| regulator-boot-on; |
| regulator-max-microvolt = <1260000>; |
| regulator-min-microvolt = <1140000>; |
| regulator-name = "ldo6"; |
| }; |
| }; |
| }; |
| }; |
| |
| &iomuxc { |
| pinctrl_ethphy_int: etnphy-intgrp { |
| fsl,pins = < |
| MX8MM_IOMUXC_ENET_RD2_GPIO1_IO28 |
| (MX8MM_FSEL_FAST | MX8MM_HYS_SCHMITT) |
| >; |
| }; |
| |
| pinctrl_ethphy_rst: etnphy-rstgrp { |
| fsl,pins = < |
| MX8MM_IOMUXC_ENET_RD3_GPIO1_IO29 |
| (MX8MM_PULL_UP | MX8MM_PULL_ENABLE) |
| >; |
| }; |
| |
| pinctrl_fec1: fec1grp { |
| fsl,pins = < |
| MX8MM_IOMUXC_ENET_MDC_ENET1_MDC |
| (MX8MM_DSE_X4 | MX8MM_PULL_UP | MX8MM_PULL_ENABLE) |
| MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO |
| (MX8MM_DSE_X4 | MX8MM_PULL_UP | MX8MM_PULL_ENABLE) |
| MX8MM_IOMUXC_ENET_TD2_ENET1_TX_CLK |
| (MX8MM_FSEL_FAST | MX8MM_SION) |
| MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 |
| (MX8MM_DSE_X6 | MX8MM_FSEL_FAST) |
| MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 |
| (MX8MM_DSE_X6 | MX8MM_FSEL_FAST) |
| MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 |
| (MX8MM_FSEL_FAST | MX8MM_HYS_SCHMITT) |
| MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 |
| (MX8MM_FSEL_FAST | MX8MM_HYS_SCHMITT) |
| MX8MM_IOMUXC_ENET_RXC_ENET1_RX_ER |
| MX8MM_FSEL_FAST |
| MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL |
| MX8MM_FSEL_FAST |
| MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL |
| (MX8MM_DSE_X6 | MX8MM_FSEL_FAST) |
| >; |
| }; |
| |
| pinctrl_i2c1: i2c1grp { |
| fsl,pins = < |
| MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL |
| MX8MM_I2C_DEFAULT |
| MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA |
| MX8MM_I2C_DEFAULT |
| >; |
| }; |
| |
| pinctrl_i2c1_gpio: i2c1-gpiogrp { |
| fsl,pins = < |
| MX8MM_IOMUXC_I2C1_SCL_GPIO5_IO14 |
| MX8MM_I2C_DEFAULT |
| MX8MM_IOMUXC_I2C1_SDA_GPIO5_IO15 |
| MX8MM_I2C_DEFAULT |
| >; |
| }; |
| |
| pinctrl_pmic: pmicgrp { |
| fsl,pins = < |
| MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 |
| (MX8MM_PULL_UP | MX8MM_HYS_SCHMITT | MX8MM_PULL_ENABLE) |
| >; |
| }; |
| |
| pinctrl_reg_3v3_etn: reg-3v3-etngrp { |
| fsl,pins = < |
| MX8MM_IOMUXC_ENET_TXC_GPIO1_IO23 |
| (MX8MM_DSE_X4 | MX8MM_PULL_UP | MX8MM_PULL_ENABLE) |
| >; |
| }; |
| |
| pinctrl_usdhc1: usdhc1grp { |
| fsl,pins = < |
| MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK |
| (MX8MM_FSEL_FAST | MX8MM_HYS_SCHMITT | MX8MM_PULL_ENABLE) |
| MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD |
| MX8MM_USDHC_DATA_DEFAULT |
| MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 |
| MX8MM_USDHC_DATA_DEFAULT |
| MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 |
| MX8MM_USDHC_DATA_DEFAULT |
| MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 |
| MX8MM_USDHC_DATA_DEFAULT |
| MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 |
| MX8MM_USDHC_DATA_DEFAULT |
| MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 |
| MX8MM_USDHC_DATA_DEFAULT |
| MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 |
| MX8MM_USDHC_DATA_DEFAULT |
| MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 |
| MX8MM_USDHC_DATA_DEFAULT |
| MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 |
| MX8MM_USDHC_DATA_DEFAULT |
| MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE |
| (MX8MM_FSEL_FAST | MX8MM_HYS_SCHMITT | MX8MM_PULL_ENABLE) |
| MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B |
| (MX8MM_DSE_X6 | MX8MM_FSEL_FAST | MX8MM_PULL_UP | MX8MM_PULL_ENABLE) |
| >; |
| }; |
| |
| pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { |
| fsl,pins = < |
| MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK |
| (MX8MM_DSE_X2 | MX8MM_FSEL_FAST | MX8MM_HYS_SCHMITT | MX8MM_PULL_ENABLE) |
| MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD |
| (MX8MM_DSE_X2 | MX8MM_USDHC_DATA_DEFAULT) |
| MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 |
| (MX8MM_DSE_X2 | MX8MM_USDHC_DATA_DEFAULT) |
| MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 |
| (MX8MM_DSE_X2 | MX8MM_USDHC_DATA_DEFAULT) |
| MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 |
| (MX8MM_DSE_X2 | MX8MM_USDHC_DATA_DEFAULT) |
| MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 |
| (MX8MM_DSE_X2 | MX8MM_USDHC_DATA_DEFAULT) |
| MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 |
| (MX8MM_DSE_X2 | MX8MM_USDHC_DATA_DEFAULT) |
| MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 |
| (MX8MM_DSE_X2 | MX8MM_USDHC_DATA_DEFAULT) |
| MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 |
| (MX8MM_DSE_X2 | MX8MM_USDHC_DATA_DEFAULT) |
| MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 |
| (MX8MM_DSE_X2 | MX8MM_USDHC_DATA_DEFAULT) |
| MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE |
| (MX8MM_DSE_X2 | MX8MM_FSEL_FAST | MX8MM_HYS_SCHMITT | MX8MM_PULL_ENABLE) |
| MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B |
| (MX8MM_DSE_X6 | MX8MM_FSEL_FAST | MX8MM_PULL_UP | MX8MM_PULL_ENABLE) |
| >; |
| }; |
| |
| pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { |
| fsl,pins = < |
| MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK |
| (MX8MM_DSE_X6 | MX8MM_FSEL_FAST | MX8MM_HYS_SCHMITT | MX8MM_PULL_ENABLE) |
| MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD |
| (MX8MM_DSE_X6 | MX8MM_USDHC_DATA_DEFAULT) |
| MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 |
| (MX8MM_DSE_X6 | MX8MM_USDHC_DATA_DEFAULT) |
| MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 |
| (MX8MM_DSE_X6 | MX8MM_USDHC_DATA_DEFAULT) |
| MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 |
| (MX8MM_DSE_X6 | MX8MM_USDHC_DATA_DEFAULT) |
| MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 |
| (MX8MM_DSE_X6 | MX8MM_USDHC_DATA_DEFAULT) |
| MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 |
| (MX8MM_DSE_X6 | MX8MM_USDHC_DATA_DEFAULT) |
| MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 |
| (MX8MM_DSE_X6 | MX8MM_USDHC_DATA_DEFAULT) |
| MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 |
| (MX8MM_DSE_X6 | MX8MM_USDHC_DATA_DEFAULT) |
| MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 |
| (MX8MM_DSE_X6 | MX8MM_USDHC_DATA_DEFAULT) |
| MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE |
| (MX8MM_DSE_X6 | MX8MM_FSEL_FAST | MX8MM_HYS_SCHMITT | MX8MM_PULL_ENABLE) |
| MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B |
| (MX8MM_DSE_X6 | MX8MM_FSEL_FAST | MX8MM_PULL_UP | MX8MM_PULL_ENABLE) |
| >; |
| }; |
| }; |
| |
| &usdhc1 { |
| assigned-clocks = <&clk IMX8MM_CLK_USDHC1>; |
| assigned-clock-rates = <400000000>; |
| bus-width = <8>; |
| non-removable; |
| pinctrl-0 = <&pinctrl_usdhc1>; |
| pinctrl-1 = <&pinctrl_usdhc1_100mhz>; |
| pinctrl-2 = <&pinctrl_usdhc1_200mhz>; |
| pinctrl-names = "default", "state_100mhz", "state_200mhz"; |
| vmmc-supply = <®_vdd_3v3>; |
| vqmmc-supply = <®_vdd_1v8>; |
| status = "okay"; |
| }; |
