| // SPDX-License-Identifier: GPL-2.0-only |
| /* |
| * Copyright (C) 2023, Intel Corporation |
| */ |
| |
| /dts-v1/; |
| #include <dt-bindings/reset/altr,rst-mgr-s10.h> |
| #include <dt-bindings/gpio/gpio.h> |
| #include <dt-bindings/interrupt-controller/arm-gic.h> |
| #include <dt-bindings/interrupt-controller/irq.h> |
| #include <dt-bindings/clock/intel,agilex5-clkmgr.h> |
| |
| / { |
| compatible = "intel,socfpga-agilex5"; |
| #address-cells = <2>; |
| #size-cells = <2>; |
| |
| reserved-memory { |
| #address-cells = <2>; |
| #size-cells = <2>; |
| ranges; |
| |
| service_reserved: svcbuffer@0 { |
| compatible = "shared-dma-pool"; |
| reg = <0x0 0x80000000 0x0 0x2000000>; |
| alignment = <0x1000>; |
| no-map; |
| }; |
| }; |
| |
| cpus { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| cpu0: cpu@0 { |
| compatible = "arm,cortex-a55"; |
| reg = <0x0>; |
| device_type = "cpu"; |
| enable-method = "psci"; |
| next-level-cache = <&L2>; |
| }; |
| |
| cpu1: cpu@1 { |
| compatible = "arm,cortex-a55"; |
| reg = <0x100>; |
| device_type = "cpu"; |
| enable-method = "psci"; |
| next-level-cache = <&L2>; |
| }; |
| |
| cpu2: cpu@2 { |
| compatible = "arm,cortex-a76"; |
| reg = <0x200>; |
| device_type = "cpu"; |
| enable-method = "psci"; |
| next-level-cache = <&L2>; |
| }; |
| |
| cpu3: cpu@3 { |
| compatible = "arm,cortex-a76"; |
| reg = <0x300>; |
| device_type = "cpu"; |
| enable-method = "psci"; |
| next-level-cache = <&L2>; |
| }; |
| |
| L2: l2-cache { |
| compatible = "cache"; |
| cache-level = <2>; |
| next-level-cache = <&L3>; |
| cache-unified; |
| }; |
| |
| L3: l3-cache { |
| compatible = "cache"; |
| cache-level = <3>; |
| cache-unified; |
| }; |
| |
| }; |
| |
| firmware { |
| svc { |
| compatible = "intel,agilex5-svc"; |
| method = "smc"; |
| memory-region = <&service_reserved>; |
| iommus = <&smmu 10>; |
| }; |
| }; |
| |
| psci { |
| compatible = "arm,psci-0.2"; |
| method = "smc"; |
| }; |
| |
| intc: interrupt-controller@1d000000 { |
| compatible = "arm,gic-v3"; |
| reg = <0x0 0x1d000000 0 0x10000>, |
| <0x0 0x1d060000 0 0x100000>; |
| ranges; |
| #interrupt-cells = <3>; |
| #address-cells = <2>; |
| #size-cells = <2>; |
| interrupt-controller; |
| interrupt-parent = <&intc>; |
| #redistributor-regions = <1>; |
| redistributor-stride = <0x0 0x20000>; |
| /* VGIC maintenance interrupt */ |
| interrupts = <GIC_PPI 25 IRQ_TYPE_LEVEL_HIGH>; |
| |
| its: msi-controller@1d040000 { |
| compatible = "arm,gic-v3-its"; |
| reg = <0x0 0x1d040000 0x0 0x20000>; |
| msi-controller; |
| #msi-cells = <1>; |
| }; |
| }; |
| |
| /* Clock tree 5 main sources*/ |
| clocks { |
| cb_intosc_hs_div2_clk: cb-intosc-hs-div2-clk { |
| #clock-cells = <0>; |
| compatible = "fixed-clock"; |
| clock-frequency = <0>; |
| }; |
| |
| cb_intosc_ls_clk: cb-intosc-ls-clk { |
| #clock-cells = <0>; |
| compatible = "fixed-clock"; |
| clock-frequency = <0>; |
| }; |
| |
| f2s_free_clk: f2s-free-clk { |
| #clock-cells = <0>; |
| compatible = "fixed-clock"; |
| clock-frequency = <0>; |
| }; |
| |
| osc1: osc1 { |
| #clock-cells = <0>; |
| compatible = "fixed-clock"; |
| clock-frequency = <0>; |
| }; |
| |
| qspi_clk: qspi-clk { |
| #clock-cells = <0>; |
| compatible = "fixed-clock"; |
| clock-frequency = <200000000>; |
| }; |
| }; |
| |
| timer { |
| compatible = "arm,armv8-timer"; |
| interrupt-parent = <&intc>; |
| interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, |
| <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, |
| <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, |
| <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; |
| }; |
| |
| usbphy0: usbphy { |
| #phy-cells = <0>; |
| compatible = "usb-nop-xceiv"; |
| }; |
| |
| pmu0: pmu { |
| compatible = "arm,armv8-pmuv3"; |
| interrupt-parent = <&intc>; |
| interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; |
| }; |
| |
| soc: soc@0 { |
| compatible = "simple-bus"; |
| ranges = <0 0 0 0xffffffff>; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| device_type = "soc"; |
| interrupt-parent = <&intc>; |
| |
| clkmgr: clock-controller@10d10000 { |
| compatible = "intel,agilex5-clkmgr"; |
| reg = <0x10d10000 0x1000>; |
| #clock-cells = <1>; |
| }; |
| |
| i2c0: i2c@10c02800 { |
| compatible = "snps,designware-i2c"; |
| reg = <0x10c02800 0x100>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; |
| resets = <&rst I2C0_RESET>; |
| clocks = <&clkmgr AGILEX5_L4_SP_CLK>; |
| status = "disabled"; |
| }; |
| |
| i2c1: i2c@10c02900 { |
| compatible = "snps,designware-i2c"; |
| reg = <0x10c02900 0x100>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; |
| resets = <&rst I2C1_RESET>; |
| clocks = <&clkmgr AGILEX5_L4_SP_CLK>; |
| status = "disabled"; |
| }; |
| |
| i2c2: i2c@10c02a00 { |
| compatible = "snps,designware-i2c"; |
| reg = <0x10c02a00 0x100>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; |
| resets = <&rst I2C2_RESET>; |
| clocks = <&clkmgr AGILEX5_L4_SP_CLK>; |
| status = "disabled"; |
| }; |
| |
| i2c3: i2c@10c02b00 { |
| compatible = "snps,designware-i2c"; |
| reg = <0x10c02b00 0x100>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; |
| resets = <&rst I2C3_RESET>; |
| clocks = <&clkmgr AGILEX5_L4_SP_CLK>; |
| status = "disabled"; |
| }; |
| |
| i2c4: i2c@10c02c00 { |
| compatible = "snps,designware-i2c"; |
| reg = <0x10c02c00 0x100>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; |
| resets = <&rst I2C4_RESET>; |
| clocks = <&clkmgr AGILEX5_L4_SP_CLK>; |
| status = "disabled"; |
| }; |
| |
| i3c0: i3c@10da0000 { |
| compatible = "altr,agilex5-dw-i3c-master", |
| "snps,dw-i3c-master-1.00a"; |
| reg = <0x10da0000 0x1000>; |
| #address-cells = <3>; |
| #size-cells = <0>; |
| interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&clkmgr AGILEX5_L4_MP_CLK>; |
| status = "disabled"; |
| }; |
| |
| i3c1: i3c@10da1000 { |
| compatible = "altr,agilex5-dw-i3c-master", |
| "snps,dw-i3c-master-1.00a"; |
| reg = <0x10da1000 0x1000>; |
| #address-cells = <3>; |
| #size-cells = <0>; |
| interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&clkmgr AGILEX5_L4_MP_CLK>; |
| status = "disabled"; |
| }; |
| |
| gpio0: gpio@10c03200 { |
| compatible = "snps,dw-apb-gpio"; |
| reg = <0x10c03200 0x100>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| resets = <&rst GPIO0_RESET>; |
| status = "disabled"; |
| |
| porta: gpio-controller@0 { |
| compatible = "snps,dw-apb-gpio-port"; |
| reg = <0>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| snps,nr-gpios = <24>; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; |
| }; |
| }; |
| |
| gpio1: gpio@10c03300 { |
| compatible = "snps,dw-apb-gpio"; |
| reg = <0x10c03300 0x100>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| resets = <&rst GPIO1_RESET>; |
| status = "disabled"; |
| |
| portb: gpio-controller@0 { |
| compatible = "snps,dw-apb-gpio-port"; |
| reg = <0>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| snps,nr-gpios = <24>; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; |
| }; |
| }; |
| |
| nand: nand-controller@10b80000 { |
| compatible = "cdns,hp-nfc"; |
| reg = <0x10b80000 0x10000>, |
| <0x10840000 0x10000>; |
| reg-names = "reg", "sdma"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&clkmgr AGILEX5_NAND_NF_CLK>; |
| clock-names = "nf_clk"; |
| cdns,board-delay-ps = <4830>; |
| iommus = <&smmu 4>; |
| dma-coherent; |
| status = "disabled"; |
| }; |
| |
| ocram: sram@0 { |
| compatible = "mmio-sram"; |
| reg = <0x00000000 0x80000>; |
| ranges = <0 0 0x80000>; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| }; |
| |
| dma: dma-bus@10db0000 { |
| compatible = "simple-bus"; |
| #address-cells = <1>; |
| #size-cells = <2>; |
| ranges = <0x00 0x10db0000 0x00 0x20000>; |
| dma-ranges = <0x00 0x00 0x100 0x00>; |
| |
| dmac0: dma-controller@0 { |
| compatible = "altr,agilex5-axi-dma", |
| "snps,axi-dma-1.01a"; |
| reg = <0x0 0x0 0x500>; |
| clocks = <&clkmgr AGILEX5_L4_MAIN_CLK>, |
| <&clkmgr AGILEX5_L4_MP_CLK>; |
| clock-names = "core-clk", "cfgr-clk"; |
| interrupt-parent = <&intc>; |
| interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; |
| #dma-cells = <1>; |
| dma-channels = <4>; |
| snps,dma-masters = <1>; |
| snps,data-width = <3>; |
| snps,block-size = <32767 32767 32767 32767>; |
| snps,priority = <0 1 2 3>; |
| snps,axi-max-burst-len = <8>; |
| iommus = <&smmu 8>; |
| }; |
| |
| dmac1: dma-controller@10000 { |
| compatible = "altr,agilex5-axi-dma", |
| "snps,axi-dma-1.01a"; |
| reg = <0x10000 0x0 0x500>; |
| clocks = <&clkmgr AGILEX5_L4_MAIN_CLK>, |
| <&clkmgr AGILEX5_L4_MP_CLK>; |
| clock-names = "core-clk", "cfgr-clk"; |
| interrupt-parent = <&intc>; |
| interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>; |
| #dma-cells = <1>; |
| dma-channels = <4>; |
| snps,dma-masters = <1>; |
| snps,data-width = <3>; |
| snps,block-size = <32767 32767 32767 32767>; |
| snps,priority = <0 1 2 3>; |
| snps,axi-max-burst-len = <8>; |
| iommus = <&smmu 9>; |
| }; |
| }; |
| |
| rst: rstmgr@10d11000 { |
| compatible = "altr,stratix10-rst-mgr", "altr,rst-mgr"; |
| reg = <0x10d11000 0x1000>; |
| #reset-cells = <1>; |
| }; |
| |
| smmu: iommu@16000000 { |
| compatible = "arm,smmu-v3"; |
| reg = <0x16000000 0x30000>; |
| interrupts = <GIC_SPI 134 IRQ_TYPE_EDGE_RISING>, |
| <GIC_SPI 129 IRQ_TYPE_EDGE_RISING>, |
| <GIC_SPI 132 IRQ_TYPE_EDGE_RISING>; |
| interrupt-names = "eventq", "gerror", "priq"; |
| dma-coherent; |
| #iommu-cells = <1>; |
| status = "disabled"; |
| }; |
| |
| spi0: spi@10da4000 { |
| compatible = "snps,dw-apb-ssi"; |
| reg = <0x10da4000 0x1000>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; |
| resets = <&rst SPIM0_RESET>; |
| reset-names = "spi"; |
| reg-io-width = <4>; |
| num-cs = <4>; |
| clocks = <&clkmgr AGILEX5_L4_MAIN_CLK>; |
| dmas = <&dmac0 16>, <&dmac0 17>; |
| dma-names = "tx", "rx"; |
| status = "disabled"; |
| |
| }; |
| |
| spi1: spi@10da5000 { |
| compatible = "snps,dw-apb-ssi"; |
| reg = <0x10da5000 0x1000>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; |
| resets = <&rst SPIM1_RESET>; |
| reset-names = "spi"; |
| reg-io-width = <4>; |
| num-cs = <4>; |
| clocks = <&clkmgr AGILEX5_L4_MAIN_CLK>; |
| dmas = <&dmac0 20>, <&dmac0 21>; |
| dma-names = "tx", "rx"; |
| status = "disabled"; |
| }; |
| |
| sysmgr: sysmgr@10d12000 { |
| compatible = "altr,sys-mgr-s10","altr,sys-mgr"; |
| reg = <0x10d12000 0x500>; |
| }; |
| |
| timer0: timer0@10c03000 { |
| compatible = "snps,dw-apb-timer"; |
| reg = <0x10c03000 0x100>; |
| interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&clkmgr AGILEX5_L4_SP_CLK>; |
| clock-names = "timer"; |
| }; |
| |
| timer1: timer1@10c03100 { |
| compatible = "snps,dw-apb-timer"; |
| reg = <0x10c03100 0x100>; |
| interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&clkmgr AGILEX5_L4_SP_CLK>; |
| clock-names = "timer"; |
| }; |
| |
| timer2: timer2@10d00000 { |
| compatible = "snps,dw-apb-timer"; |
| reg = <0x10d00000 0x100>; |
| interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&clkmgr AGILEX5_L4_SP_CLK>; |
| clock-names = "timer"; |
| }; |
| |
| timer3: timer3@10d00100 { |
| compatible = "snps,dw-apb-timer"; |
| reg = <0x10d00100 0x100>; |
| interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&clkmgr AGILEX5_L4_SP_CLK>; |
| clock-names = "timer"; |
| }; |
| |
| uart0: serial@10c02000 { |
| compatible = "snps,dw-apb-uart"; |
| reg = <0x10c02000 0x100>; |
| interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; |
| reg-shift = <2>; |
| reg-io-width = <4>; |
| resets = <&rst UART0_RESET>; |
| status = "disabled"; |
| clocks = <&clkmgr AGILEX5_L4_SP_CLK>; |
| }; |
| |
| uart1: serial@10c02100 { |
| compatible = "snps,dw-apb-uart"; |
| reg = <0x10c02100 0x100>; |
| interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; |
| reg-shift = <2>; |
| reg-io-width = <4>; |
| resets = <&rst UART1_RESET>; |
| status = "disabled"; |
| clocks = <&clkmgr AGILEX5_L4_SP_CLK>; |
| }; |
| |
| usb0: usb@10b00000 { |
| compatible = "snps,dwc2"; |
| reg = <0x10b00000 0x40000>; |
| interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; |
| phys = <&usbphy0>; |
| phy-names = "usb2-phy"; |
| resets = <&rst USB0_RESET>, <&rst USB0_OCP_RESET>; |
| reset-names = "dwc2", "dwc2-ecc"; |
| iommus = <&smmu 6>; |
| clocks = <&clkmgr AGILEX5_USB2OTG_HCLK>; |
| clock-names = "otg"; |
| status = "disabled"; |
| }; |
| |
| watchdog0: watchdog@10d00200 { |
| compatible = "snps,dw-wdt"; |
| reg = <0x10d00200 0x100>; |
| interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; |
| resets = <&rst WATCHDOG0_RESET>; |
| clocks = <&clkmgr AGILEX5_L4_SYS_FREE_CLK>; |
| status = "disabled"; |
| }; |
| |
| watchdog1: watchdog@10d00300 { |
| compatible = "snps,dw-wdt"; |
| reg = <0x10d00300 0x100>; |
| interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; |
| resets = <&rst WATCHDOG1_RESET>; |
| clocks = <&clkmgr AGILEX5_L4_SYS_FREE_CLK>; |
| status = "disabled"; |
| }; |
| |
| watchdog2: watchdog@10d00400 { |
| compatible = "snps,dw-wdt"; |
| reg = <0x10d00400 0x100>; |
| interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; |
| resets = <&rst WATCHDOG2_RESET>; |
| clocks = <&clkmgr AGILEX5_L4_SYS_FREE_CLK>; |
| status = "disabled"; |
| }; |
| |
| watchdog3: watchdog@10d00500 { |
| compatible = "snps,dw-wdt"; |
| reg = <0x10d00500 0x100>; |
| interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; |
| resets = <&rst WATCHDOG3_RESET>; |
| clocks = <&clkmgr AGILEX5_L4_SYS_FREE_CLK>; |
| status = "disabled"; |
| }; |
| |
| watchdog4: watchdog@10d00600 { |
| compatible = "snps,dw-wdt"; |
| reg = <0x10d00600 0x100>; |
| interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>; |
| resets = <&rst WATCHDOG4_RESET>; |
| clocks = <&clkmgr AGILEX5_L4_SYS_FREE_CLK>; |
| status = "disabled"; |
| }; |
| |
| qspi: spi@108d2000 { |
| compatible = "intel,socfpga-qspi", "cdns,qspi-nor"; |
| reg = <0x108d2000 0x100>, |
| <0x10900000 0x100000>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; |
| cdns,fifo-depth = <128>; |
| cdns,fifo-width = <4>; |
| cdns,trigger-address = <0x00000000>; |
| clocks = <&qspi_clk>; |
| status = "disabled"; |
| }; |
| |
| gmac0: ethernet@10810000 { |
| compatible = "altr,socfpga-stmmac-agilex5", |
| "snps,dwxgmac-2.10"; |
| reg = <0x10810000 0x3500>; |
| interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; |
| interrupt-names = "macirq"; |
| resets = <&rst EMAC0_RESET>, <&rst EMAC0_OCP_RESET>; |
| reset-names = "stmmaceth", "ahb"; |
| clocks = <&clkmgr AGILEX5_EMAC0_CLK>, |
| <&clkmgr AGILEX5_EMAC_PTP_CLK>; |
| clock-names = "stmmaceth", "ptp_ref"; |
| mac-address = [00 00 00 00 00 00]; |
| tx-fifo-depth = <32768>; |
| rx-fifo-depth = <16384>; |
| snps,multicast-filter-bins = <64>; |
| snps,perfect-filter-entries = <64>; |
| snps,axi-config = <&stmmac_axi_emac0_setup>; |
| snps,mtl-rx-config = <&mtl_rx_emac0_setup>; |
| snps,mtl-tx-config = <&mtl_tx_emac0_setup>; |
| snps,pbl = <32>; |
| snps,tso; |
| altr,sysmgr-syscon = <&sysmgr 0x44 0>; |
| snps,clk-csr = <0>; |
| iommus = <&smmu 1>; |
| status = "disabled"; |
| |
| stmmac_axi_emac0_setup: stmmac-axi-config { |
| snps,wr_osr_lmt = <31>; |
| snps,rd_osr_lmt = <31>; |
| snps,blen = <0 0 0 32 16 8 4>; |
| }; |
| |
| mtl_rx_emac0_setup: rx-queues-config { |
| snps,rx-queues-to-use = <8>; |
| snps,rx-sched-sp; |
| queue0 { |
| snps,dcb-algorithm; |
| snps,map-to-dma-channel = <0x0>; |
| }; |
| queue1 { |
| snps,dcb-algorithm; |
| snps,map-to-dma-channel = <0x1>; |
| }; |
| queue2 { |
| snps,dcb-algorithm; |
| snps,map-to-dma-channel = <0x2>; |
| }; |
| queue3 { |
| snps,dcb-algorithm; |
| snps,map-to-dma-channel = <0x3>; |
| }; |
| queue4 { |
| snps,dcb-algorithm; |
| snps,map-to-dma-channel = <0x4>; |
| }; |
| queue5 { |
| snps,dcb-algorithm; |
| snps,map-to-dma-channel = <0x5>; |
| }; |
| queue6 { |
| snps,dcb-algorithm; |
| snps,map-to-dma-channel = <0x6>; |
| }; |
| queue7 { |
| snps,dcb-algorithm; |
| snps,map-to-dma-channel = <0x7>; |
| }; |
| }; |
| |
| mtl_tx_emac0_setup: tx-queues-config { |
| snps,tx-queues-to-use = <8>; |
| snps,tx-sched-wrr; |
| queue0 { |
| snps,weight = <0x09>; |
| snps,dcb-algorithm; |
| }; |
| queue1 { |
| snps,weight = <0x0a>; |
| snps,dcb-algorithm; |
| }; |
| queue2 { |
| snps,weight = <0x0b>; |
| snps,coe-unsupported; |
| snps,dcb-algorithm; |
| }; |
| queue3 { |
| snps,weight = <0x0c>; |
| snps,coe-unsupported; |
| snps,dcb-algorithm; |
| }; |
| queue4 { |
| snps,weight = <0x0d>; |
| snps,coe-unsupported; |
| snps,dcb-algorithm; |
| }; |
| queue5 { |
| snps,weight = <0x0e>; |
| snps,coe-unsupported; |
| snps,dcb-algorithm; |
| }; |
| queue6 { |
| snps,weight = <0x0f>; |
| snps,coe-unsupported; |
| snps,dcb-algorithm; |
| }; |
| queue7 { |
| snps,weight = <0x10>; |
| snps,coe-unsupported; |
| snps,dcb-algorithm; |
| }; |
| }; |
| }; |
| |
| gmac1: ethernet@10820000 { |
| compatible = "altr,socfpga-stmmac-agilex5", |
| "snps,dwxgmac-2.10"; |
| reg = <0x10820000 0x3500>; |
| interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>; |
| interrupt-names = "macirq"; |
| resets = <&rst EMAC1_RESET>, <&rst EMAC1_OCP_RESET>; |
| reset-names = "stmmaceth", "ahb"; |
| clocks = <&clkmgr AGILEX5_EMAC1_CLK>, |
| <&clkmgr AGILEX5_EMAC_PTP_CLK>; |
| clock-names = "stmmaceth", "ptp_ref"; |
| mac-address = [00 00 00 00 00 00]; |
| tx-fifo-depth = <32768>; |
| rx-fifo-depth = <16384>; |
| snps,multicast-filter-bins = <64>; |
| snps,perfect-filter-entries = <64>; |
| snps,axi-config = <&stmmac_axi_emac1_setup>; |
| snps,mtl-rx-config = <&mtl_rx_emac1_setup>; |
| snps,mtl-tx-config = <&mtl_tx_emac1_setup>; |
| snps,pbl = <32>; |
| snps,tso; |
| altr,sysmgr-syscon = <&sysmgr 0x48 0>; |
| snps,clk-csr = <0>; |
| iommus = <&smmu 2>; |
| status = "disabled"; |
| |
| stmmac_axi_emac1_setup: stmmac-axi-config { |
| snps,wr_osr_lmt = <31>; |
| snps,rd_osr_lmt = <31>; |
| snps,blen = <0 0 0 32 16 8 4>; |
| }; |
| |
| mtl_rx_emac1_setup: rx-queues-config { |
| snps,rx-queues-to-use = <8>; |
| snps,rx-sched-sp; |
| queue0 { |
| snps,dcb-algorithm; |
| snps,map-to-dma-channel = <0x0>; |
| }; |
| queue1 { |
| snps,dcb-algorithm; |
| snps,map-to-dma-channel = <0x1>; |
| }; |
| queue2 { |
| snps,dcb-algorithm; |
| snps,map-to-dma-channel = <0x2>; |
| }; |
| queue3 { |
| snps,dcb-algorithm; |
| snps,map-to-dma-channel = <0x3>; |
| }; |
| queue4 { |
| snps,dcb-algorithm; |
| snps,map-to-dma-channel = <0x4>; |
| }; |
| queue5 { |
| snps,dcb-algorithm; |
| snps,map-to-dma-channel = <0x5>; |
| }; |
| queue6 { |
| snps,dcb-algorithm; |
| snps,map-to-dma-channel = <0x6>; |
| }; |
| queue7 { |
| snps,dcb-algorithm; |
| snps,map-to-dma-channel = <0x7>; |
| }; |
| }; |
| |
| mtl_tx_emac1_setup: tx-queues-config { |
| snps,tx-queues-to-use = <8>; |
| snps,tx-sched-wrr; |
| queue0 { |
| snps,weight = <0x09>; |
| snps,dcb-algorithm; |
| }; |
| queue1 { |
| snps,weight = <0x0a>; |
| snps,dcb-algorithm; |
| }; |
| queue2 { |
| snps,weight = <0x0b>; |
| snps,coe-unsupported; |
| snps,dcb-algorithm; |
| }; |
| queue3 { |
| snps,weight = <0x0c>; |
| snps,coe-unsupported; |
| snps,dcb-algorithm; |
| }; |
| queue4 { |
| snps,weight = <0x0d>; |
| snps,coe-unsupported; |
| snps,dcb-algorithm; |
| }; |
| queue5 { |
| snps,weight = <0x0e>; |
| snps,coe-unsupported; |
| snps,dcb-algorithm; |
| }; |
| queue6 { |
| snps,weight = <0x0f>; |
| snps,coe-unsupported; |
| snps,dcb-algorithm; |
| }; |
| queue7 { |
| snps,weight = <0x10>; |
| snps,coe-unsupported; |
| snps,dcb-algorithm; |
| }; |
| }; |
| }; |
| |
| gmac2: ethernet@10830000 { |
| compatible = "altr,socfpga-stmmac-agilex5", |
| "snps,dwxgmac-2.10"; |
| reg = <0x10830000 0x3500>; |
| interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>; |
| interrupt-names = "macirq"; |
| resets = <&rst EMAC2_RESET>, <&rst EMAC2_OCP_RESET>; |
| reset-names = "stmmaceth", "ahb"; |
| clocks = <&clkmgr AGILEX5_EMAC2_CLK>, |
| <&clkmgr AGILEX5_EMAC_PTP_CLK>; |
| clock-names = "stmmaceth", "ptp_ref"; |
| mac-address = [00 00 00 00 00 00]; |
| tx-fifo-depth = <32768>; |
| rx-fifo-depth = <16384>; |
| snps,multicast-filter-bins = <64>; |
| snps,perfect-filter-entries = <64>; |
| snps,axi-config = <&stmmac_axi_emac2_setup>; |
| snps,mtl-rx-config = <&mtl_rx_emac2_setup>; |
| snps,mtl-tx-config = <&mtl_tx_emac2_setup>; |
| snps,pbl = <32>; |
| snps,tso; |
| altr,sysmgr-syscon = <&sysmgr 0x4c 0>; |
| snps,clk-csr = <0>; |
| iommus = <&smmu 3>; |
| status = "disabled"; |
| |
| stmmac_axi_emac2_setup: stmmac-axi-config { |
| snps,wr_osr_lmt = <31>; |
| snps,rd_osr_lmt = <31>; |
| snps,blen = <0 0 0 32 16 8 4>; |
| }; |
| |
| mtl_rx_emac2_setup: rx-queues-config { |
| snps,rx-queues-to-use = <8>; |
| snps,rx-sched-sp; |
| queue0 { |
| snps,dcb-algorithm; |
| snps,map-to-dma-channel = <0x0>; |
| }; |
| queue1 { |
| snps,dcb-algorithm; |
| snps,map-to-dma-channel = <0x1>; |
| }; |
| queue2 { |
| snps,dcb-algorithm; |
| snps,map-to-dma-channel = <0x2>; |
| }; |
| queue3 { |
| snps,dcb-algorithm; |
| snps,map-to-dma-channel = <0x3>; |
| }; |
| queue4 { |
| snps,dcb-algorithm; |
| snps,map-to-dma-channel = <0x4>; |
| }; |
| queue5 { |
| snps,dcb-algorithm; |
| snps,map-to-dma-channel = <0x5>; |
| }; |
| queue6 { |
| snps,dcb-algorithm; |
| snps,map-to-dma-channel = <0x6>; |
| }; |
| queue7 { |
| snps,dcb-algorithm; |
| snps,map-to-dma-channel = <0x7>; |
| }; |
| }; |
| |
| mtl_tx_emac2_setup: tx-queues-config { |
| snps,tx-queues-to-use = <8>; |
| snps,tx-sched-wrr; |
| queue0 { |
| snps,weight = <0x09>; |
| snps,dcb-algorithm; |
| }; |
| queue1 { |
| snps,weight = <0x0a>; |
| snps,dcb-algorithm; |
| }; |
| queue2 { |
| snps,weight = <0x0b>; |
| snps,coe-unsupported; |
| snps,dcb-algorithm; |
| }; |
| queue3 { |
| snps,weight = <0x0c>; |
| snps,coe-unsupported; |
| snps,dcb-algorithm; |
| }; |
| queue4 { |
| snps,weight = <0x0d>; |
| snps,coe-unsupported; |
| snps,dcb-algorithm; |
| }; |
| queue5 { |
| snps,weight = <0x0e>; |
| snps,coe-unsupported; |
| snps,dcb-algorithm; |
| }; |
| queue6 { |
| snps,weight = <0x0f>; |
| snps,coe-unsupported; |
| snps,dcb-algorithm; |
| }; |
| queue7 { |
| snps,weight = <0x10>; |
| snps,coe-unsupported; |
| snps,dcb-algorithm; |
| }; |
| }; |
| }; |
| |
| pmu0_tcu: pmu@16002000 { |
| compatible = "arm,smmu-v3-pmcg"; |
| reg = <0x16002000 0x1000>, |
| <0x16022000 0x1000>; |
| interrupt-parent = <&intc>; |
| interrupts = <GIC_SPI 136 IRQ_TYPE_EDGE_RISING>; |
| }; |
| |
| pmu0_tbu0: pmu@16042000 { |
| compatible = "arm,smmu-v3-pmcg"; |
| reg = <0x16042000 0x1000>, |
| <0x16052000 0x1000>; |
| interrupt-parent = <&intc>; |
| interrupts = <GIC_SPI 138 IRQ_TYPE_EDGE_RISING>; |
| }; |
| |
| pmu0_tbu1: pmu@16062000 { |
| compatible = "arm,smmu-v3-pmcg"; |
| reg = <0x16062000 0x1000>, |
| <0x16072000 0x1000>; |
| interrupt-parent = <&intc>; |
| interrupts = <GIC_SPI 140 IRQ_TYPE_EDGE_RISING>; |
| }; |
| |
| pmu0_tbu2: pmu@16082000 { |
| compatible = "arm,smmu-v3-pmcg"; |
| reg = <0x16082000 0x1000>, |
| <0x16092000 0x1000>; |
| interrupt-parent = <&intc>; |
| interrupts = <GIC_SPI 142 IRQ_TYPE_EDGE_RISING>; |
| }; |
| |
| pmu0_tbu3: pmu@160a2000 { |
| compatible = "arm,smmu-v3-pmcg"; |
| reg = <0x160a2000 0x1000>, |
| <0x160b2000 0x1000>; |
| interrupt-parent = <&intc>; |
| interrupts = <GIC_SPI 144 IRQ_TYPE_EDGE_RISING>; |
| }; |
| |
| pmu0_tbu4: pmu@160c2000 { |
| compatible = "arm,smmu-v3-pmcg"; |
| reg = <0x160c2000 0x1000>, |
| <0x160d2000 0x1000>; |
| interrupt-parent = <&intc>; |
| interrupts = <GIC_SPI 146 IRQ_TYPE_EDGE_RISING>; |
| }; |
| |
| pmu0_tbu5: pmu@160e2000 { |
| compatible = "arm,smmu-v3-pmcg"; |
| reg = <0x160e2000 0x1000>, |
| <0x160f2000 0x1000>; |
| interrupt-parent = <&intc>; |
| interrupts = <GIC_SPI 150 IRQ_TYPE_EDGE_RISING>; |
| }; |
| }; |
| }; |
