arch/arm64/boot/dts/renesas/r8a78000.dtsi

// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
/*
 * Device Tree Source for the R-Car X5H (R8A78000) SoC
 *
 * Copyright (C) 2025 Renesas Electronics Corp.
 */

#include <dt-bindings/interrupt-controller/arm-gic.h>

/ {
	compatible = "renesas,r8a78000";
	#address-cells = <2>;
	#size-cells = <2>;
	interrupt-parent = <&gic>;

	cpus {
		#address-cells = <2>;
		#size-cells = <0>;

		cpu-map {
			cluster0 {
				core0 {
					cpu = <&a720_0>;
				};
				core1 {
					cpu = <&a720_1>;
				};
				core2 {
					cpu = <&a720_2>;
				};
				core3 {
					cpu = <&a720_3>;
				};
			};

			cluster1 {
				core0 {
					cpu = <&a720_4>;
				};
				core1 {
					cpu = <&a720_5>;
				};
				core2 {
					cpu = <&a720_6>;
				};
				core3 {
					cpu = <&a720_7>;
				};
			};

			cluster2 {
				core0 {
					cpu = <&a720_8>;
				};
				core1 {
					cpu = <&a720_9>;
				};
				core2 {
					cpu = <&a720_10>;
				};
				core3 {
					cpu = <&a720_11>;
				};
			};

			cluster3 {
				core0 {
					cpu = <&a720_12>;
				};
				core1 {
					cpu = <&a720_13>;
				};
				core2 {
					cpu = <&a720_14>;
				};
				core3 {
					cpu = <&a720_15>;
				};
			};

			cluster4 {
				core0 {
					cpu = <&a720_16>;
				};
				core1 {
					cpu = <&a720_17>;
				};
				core2 {
					cpu = <&a720_18>;
				};
				core3 {
					cpu = <&a720_19>;
				};
			};

			cluster5 {
				core0 {
					cpu = <&a720_20>;
				};
				core1 {
					cpu = <&a720_21>;
				};
				core2 {
					cpu = <&a720_22>;
				};
				core3 {
					cpu = <&a720_23>;
				};
			};

			cluster6 {
				core0 {
					cpu = <&a720_24>;
				};
				core1 {
					cpu = <&a720_25>;
				};
				core2 {
					cpu = <&a720_26>;
				};
				core3 {
					cpu = <&a720_27>;
				};
			};

			cluster7 {
				core0 {
					cpu = <&a720_28>;
				};
				core1 {
					cpu = <&a720_29>;
				};
				core2 {
					cpu = <&a720_30>;
				};
				core3 {
					cpu = <&a720_31>;
				};
			};
		};

		a720_0: cpu@0 {
			compatible = "arm,cortex-a720ae";
			reg = <0x0 0x0>;
			device_type = "cpu";
			next-level-cache = <&L2_CA720_0>;
		};

		a720_1: cpu@100 {
			compatible = "arm,cortex-a720ae";
			reg = <0x0 0x100>;
			device_type = "cpu";
			next-level-cache = <&L2_CA720_1>;
		};

		a720_2: cpu@200 {
			compatible = "arm,cortex-a720ae";
			reg = <0x0 0x200>;
			device_type = "cpu";
			next-level-cache = <&L2_CA720_2>;
		};

		a720_3: cpu@300 {
			compatible = "arm,cortex-a720ae";
			reg = <0x0 0x300>;
			device_type = "cpu";
			next-level-cache = <&L2_CA720_3>;
		};

		a720_4: cpu@10000 {
			compatible = "arm,cortex-a720ae";
			reg = <0x0 0x10000>;
			device_type = "cpu";
			next-level-cache = <&L2_CA720_4>;
		};

		a720_5: cpu@10100 {
			compatible = "arm,cortex-a720ae";
			reg = <0x0 0x10100>;
			device_type = "cpu";
			next-level-cache = <&L2_CA720_5>;
		};

		a720_6: cpu@10200 {
			compatible = "arm,cortex-a720ae";
			reg = <0x0 0x10200>;
			device_type = "cpu";
			next-level-cache = <&L2_CA720_6>;
		};

		a720_7: cpu@10300 {
			compatible = "arm,cortex-a720ae";
			reg = <0x0 0x10300>;
			device_type = "cpu";
			next-level-cache = <&L2_CA720_7>;
		};

		a720_8: cpu@20000 {
			compatible = "arm,cortex-a720ae";
			reg = <0x0 0x20000>;
			device_type = "cpu";
			next-level-cache = <&L2_CA720_8>;
		};

		a720_9: cpu@20100 {
			compatible = "arm,cortex-a720ae";
			reg = <0x0 0x20100>;
			device_type = "cpu";
			next-level-cache = <&L2_CA720_9>;
		};

		a720_10: cpu@20200 {
			compatible = "arm,cortex-a720ae";
			reg = <0x0 0x20200>;
			device_type = "cpu";
			next-level-cache = <&L2_CA720_10>;
		};

		a720_11: cpu@20300 {
			compatible = "arm,cortex-a720ae";
			reg = <0x0 0x20300>;
			device_type = "cpu";
			next-level-cache = <&L2_CA720_11>;
		};

		a720_12: cpu@30000 {
			compatible = "arm,cortex-a720ae";
			reg = <0x0 0x30000>;
			device_type = "cpu";
			next-level-cache = <&L2_CA720_12>;
		};

		a720_13: cpu@30100 {
			compatible = "arm,cortex-a720ae";
			reg = <0x0 0x30100>;
			device_type = "cpu";
			next-level-cache = <&L2_CA720_13>;
		};

		a720_14: cpu@30200 {
			compatible = "arm,cortex-a720ae";
			reg = <0x0 0x30200>;
			device_type = "cpu";
			next-level-cache = <&L2_CA720_14>;
		};

		a720_15: cpu@30300 {
			compatible = "arm,cortex-a720ae";
			reg = <0x0 0x30300>;
			device_type = "cpu";
			next-level-cache = <&L2_CA720_15>;
		};

		a720_16: cpu@40000 {
			compatible = "arm,cortex-a720ae";
			reg = <0x0 0x40000>;
			device_type = "cpu";
			next-level-cache = <&L2_CA720_16>;
		};

		a720_17: cpu@40100 {
			compatible = "arm,cortex-a720ae";
			reg = <0x0 0x40100>;
			device_type = "cpu";
			next-level-cache = <&L2_CA720_17>;
		};

		a720_18: cpu@40200 {
			compatible = "arm,cortex-a720ae";
			reg = <0x0 0x40200>;
			device_type = "cpu";
			next-level-cache = <&L2_CA720_18>;
		};

		a720_19: cpu@40300 {
			compatible = "arm,cortex-a720ae";
			reg = <0x0 0x40300>;
			device_type = "cpu";
			next-level-cache = <&L2_CA720_19>;
		};

		a720_20: cpu@50000 {
			compatible = "arm,cortex-a720ae";
			reg = <0x0 0x50000>;
			device_type = "cpu";
			next-level-cache = <&L2_CA720_20>;
		};

		a720_21: cpu@50100 {
			compatible = "arm,cortex-a720ae";
			reg = <0x0 0x50100>;
			device_type = "cpu";
			next-level-cache = <&L2_CA720_21>;
		};

		a720_22: cpu@50200 {
			compatible = "arm,cortex-a720ae";
			reg = <0x0 0x50200>;
			device_type = "cpu";
			next-level-cache = <&L2_CA720_22>;
		};

		a720_23: cpu@50300 {
			compatible = "arm,cortex-a720ae";
			reg = <0x0 0x50300>;
			device_type = "cpu";
			next-level-cache = <&L2_CA720_23>;
		};

		a720_24: cpu@60000 {
			compatible = "arm,cortex-a720ae";
			reg = <0x0 0x60000>;
			device_type = "cpu";
			next-level-cache = <&L2_CA720_24>;
		};

		a720_25: cpu@60100 {
			compatible = "arm,cortex-a720ae";
			reg = <0x0 0x60100>;
			device_type = "cpu";
			next-level-cache = <&L2_CA720_25>;
		};

		a720_26: cpu@60200 {
			compatible = "arm,cortex-a720ae";
			reg = <0x0 0x60200>;
			device_type = "cpu";
			next-level-cache = <&L2_CA720_26>;
		};

		a720_27: cpu@60300 {
			compatible = "arm,cortex-a720ae";
			reg = <0x0 0x60300>;
			device_type = "cpu";
			next-level-cache = <&L2_CA720_27>;
		};

		a720_28: cpu@70000 {
			compatible = "arm,cortex-a720ae";
			reg = <0x0 0x70000>;
			device_type = "cpu";
			next-level-cache = <&L2_CA720_28>;
		};

		a720_29: cpu@70100 {
			compatible = "arm,cortex-a720ae";
			reg = <0x0 0x70100>;
			device_type = "cpu";
			next-level-cache = <&L2_CA720_29>;
		};

		a720_30: cpu@70200 {
			compatible = "arm,cortex-a720ae";
			reg = <0x0 0x70200>;
			device_type = "cpu";
			next-level-cache = <&L2_CA720_30>;
		};

		a720_31: cpu@70300 {
			compatible = "arm,cortex-a720ae";
			reg = <0x0 0x70300>;
			device_type = "cpu";
			next-level-cache = <&L2_CA720_31>;
		};

		L2_CA720_0: cache-controller-200 {
			compatible = "cache";
			cache-unified;
			cache-level = <2>;
			next-level-cache = <&L3_CA720_0>;
		};

		L2_CA720_1: cache-controller-201 {
			compatible = "cache";
			cache-unified;
			cache-level = <2>;
			next-level-cache = <&L3_CA720_0>;
		};

		L2_CA720_2: cache-controller-202 {
			compatible = "cache";
			cache-unified;
			cache-level = <2>;
			next-level-cache = <&L3_CA720_0>;
		};

		L2_CA720_3: cache-controller-203 {
			compatible = "cache";
			cache-unified;
			cache-level = <2>;
			next-level-cache = <&L3_CA720_0>;
		};

		L2_CA720_4: cache-controller-204 {
			compatible = "cache";
			cache-unified;
			cache-level = <2>;
			next-level-cache = <&L3_CA720_1>;
		};

		L2_CA720_5: cache-controller-205 {
			compatible = "cache";
			cache-unified;
			cache-level = <2>;
			next-level-cache = <&L3_CA720_1>;
		};

		L2_CA720_6: cache-controller-206 {
			compatible = "cache";
			cache-unified;
			cache-level = <2>;
			next-level-cache = <&L3_CA720_1>;
		};

		L2_CA720_7: cache-controller-207 {
			compatible = "cache";
			cache-unified;
			cache-level = <2>;
			next-level-cache = <&L3_CA720_1>;
		};

		L2_CA720_8: cache-controller-208 {
			compatible = "cache";
			cache-unified;
			cache-level = <2>;
			next-level-cache = <&L3_CA720_2>;
		};

		L2_CA720_9: cache-controller-209 {
			compatible = "cache";
			cache-unified;
			cache-level = <2>;
			next-level-cache = <&L3_CA720_2>;
		};

		L2_CA720_10: cache-controller-210 {
			compatible = "cache";
			cache-unified;
			cache-level = <2>;
			next-level-cache = <&L3_CA720_2>;
		};

		L2_CA720_11: cache-controller-211 {
			compatible = "cache";
			cache-unified;
			cache-level = <2>;
			next-level-cache = <&L3_CA720_2>;
		};

		L2_CA720_12: cache-controller-212 {
			compatible = "cache";
			cache-unified;
			cache-level = <2>;
			next-level-cache = <&L3_CA720_3>;
		};

		L2_CA720_13: cache-controller-213 {
			compatible = "cache";
			cache-unified;
			cache-level = <2>;
			next-level-cache = <&L3_CA720_3>;
		};

		L2_CA720_14: cache-controller-214 {
			compatible = "cache";
			cache-unified;
			cache-level = <2>;
			next-level-cache = <&L3_CA720_3>;
		};

		L2_CA720_15: cache-controller-215 {
			compatible = "cache";
			cache-unified;
			cache-level = <2>;
			next-level-cache = <&L3_CA720_3>;
		};

		L2_CA720_16: cache-controller-216 {
			compatible = "cache";
			cache-unified;
			cache-level = <2>;
			next-level-cache = <&L3_CA720_4>;
		};

		L2_CA720_17: cache-controller-217 {
			compatible = "cache";
			cache-unified;
			cache-level = <2>;
			next-level-cache = <&L3_CA720_4>;
		};

		L2_CA720_18: cache-controller-218 {
			compatible = "cache";
			cache-unified;
			cache-level = <2>;
			next-level-cache = <&L3_CA720_4>;
		};

		L2_CA720_19: cache-controller-219 {
			compatible = "cache";
			cache-unified;
			cache-level = <2>;
			next-level-cache = <&L3_CA720_4>;
		};

		L2_CA720_20: cache-controller-220 {
			compatible = "cache";
			cache-unified;
			cache-level = <2>;
			next-level-cache = <&L3_CA720_5>;
		};

		L2_CA720_21: cache-controller-221 {
			compatible = "cache";
			cache-unified;
			cache-level = <2>;
			next-level-cache = <&L3_CA720_5>;
		};

		L2_CA720_22: cache-controller-222 {
			compatible = "cache";
			cache-unified;
			cache-level = <2>;
			next-level-cache = <&L3_CA720_5>;
		};

		L2_CA720_23: cache-controller-223 {
			compatible = "cache";
			cache-unified;
			cache-level = <2>;
			next-level-cache = <&L3_CA720_5>;
		};

		L2_CA720_24: cache-controller-224 {
			compatible = "cache";
			cache-unified;
			cache-level = <2>;
			next-level-cache = <&L3_CA720_6>;
		};

		L2_CA720_25: cache-controller-225 {
			compatible = "cache";
			cache-unified;
			cache-level = <2>;
			next-level-cache = <&L3_CA720_6>;
		};

		L2_CA720_26: cache-controller-226 {
			compatible = "cache";
			cache-unified;
			cache-level = <2>;
			next-level-cache = <&L3_CA720_6>;
		};

		L2_CA720_27: cache-controller-227 {
			compatible = "cache";
			cache-unified;
			cache-level = <2>;
			next-level-cache = <&L3_CA720_6>;
		};

		L2_CA720_28: cache-controller-228 {
			compatible = "cache";
			cache-unified;
			cache-level = <2>;
			next-level-cache = <&L3_CA720_7>;
		};

		L2_CA720_29: cache-controller-229 {
			compatible = "cache";
			cache-unified;
			cache-level = <2>;
			next-level-cache = <&L3_CA720_7>;
		};

		L2_CA720_30: cache-controller-230 {
			compatible = "cache";
			cache-unified;
			cache-level = <2>;
			next-level-cache = <&L3_CA720_7>;
		};

		L2_CA720_31: cache-controller-231 {
			compatible = "cache";
			cache-unified;
			cache-level = <2>;
			next-level-cache = <&L3_CA720_7>;
		};

		L3_CA720_0: cache-controller-30 {
			compatible = "cache";
			cache-unified;
			cache-level = <3>;
		};

		L3_CA720_1: cache-controller-31 {
			compatible = "cache";
			cache-unified;
			cache-level = <3>;
		};

		L3_CA720_2: cache-controller-32 {
			compatible = "cache";
			cache-unified;
			cache-level = <3>;
		};

		L3_CA720_3: cache-controller-33 {
			compatible = "cache";
			cache-unified;
			cache-level = <3>;
		};

		L3_CA720_4: cache-controller-34 {
			compatible = "cache";
			cache-unified;
			cache-level = <3>;
		};

		L3_CA720_5: cache-controller-35 {
			compatible = "cache";
			cache-unified;
			cache-level = <3>;
		};

		L3_CA720_6: cache-controller-36 {
			compatible = "cache";
			cache-unified;
			cache-level = <3>;
		};

		L3_CA720_7: cache-controller-37 {
			compatible = "cache";
			cache-unified;
			cache-level = <3>;
		};
	};

	/*
	 * In the early phase, there is no clock control support,
	 * so assume that the clocks are enabled by default.
	 * Therefore, dummy clocks are used.
	 */
	dummy_clk_sgasyncd16: dummy-clk-sgasyncd16 {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <66666000>;
	};

	dummy_clk_sgasyncd4: dummy-clk-sgasyncd4 {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <266660000>;
	};

	extal_clk: extal-clk {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		/* clock-frequency must be set on board */
	};

	extalr_clk: extalr-clk {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		/* clock-frequency must be set on board */
	};

	psci {
		compatible = "arm,psci-1.0";
		method = "smc";
	};

	/* External SCIF clock - to be overridden by boards that provide it */
	scif_clk: scif-clk {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <0>; /* optional */
	};

	soc: soc {
		compatible = "simple-bus";
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		mfis: system-controller@189e0000 {
			compatible = "renesas,r8a78000-mfis";
			reg = <0 0x189e0000 0 0x1000>, <0 0x18800000 0 0x40000>;
			reg-names = "common", "mboxes";
			interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "ch0i", "ch0e", "ch1i", "ch1e", "ch2i", "ch2e", "ch3i", "ch3e",
					  "ch4i", "ch4e", "ch5i", "ch5e", "ch6i", "ch6e", "ch7i", "ch7e",
					  "ch8i", "ch8e", "ch9i", "ch9e", "ch10i", "ch10e", "ch11i", "ch11e",
					  "ch12i", "ch12e", "ch13i", "ch13e", "ch14i", "ch14e", "ch15i", "ch15e",
					  "ch16i", "ch16e", "ch17i", "ch17e", "ch18i", "ch18e", "ch19i", "ch19e",
					  "ch20i", "ch20e", "ch21i", "ch21e", "ch22i", "ch22e", "ch23i", "ch23e",
					  "ch24i", "ch24e", "ch25i", "ch25e", "ch26i", "ch26e", "ch27i", "ch27e",
					  "ch28i", "ch28e", "ch29i", "ch29e", "ch30i", "ch30e", "ch31i", "ch31e",
					  "ch32i", "ch32e", "ch33i", "ch33e", "ch34i", "ch34e", "ch35i", "ch35e",
					  "ch36i", "ch36e", "ch37i", "ch37e", "ch38i", "ch38e", "ch39i", "ch39e",
					  "ch40i", "ch40e", "ch41i", "ch41e", "ch42i", "ch42e", "ch43i", "ch43e",
					  "ch44i", "ch44e", "ch45i", "ch45e", "ch46i", "ch46e", "ch47i", "ch47e",
					  "ch48i", "ch48e", "ch49i", "ch49e", "ch50i", "ch50e", "ch51i", "ch51e",
					  "ch52i", "ch52e", "ch53i", "ch53e", "ch54i", "ch54e", "ch55i", "ch55e",
					  "ch56i", "ch56e", "ch57i", "ch57e", "ch58i", "ch58e", "ch59i", "ch59e",
					  "ch60i", "ch60e", "ch61i", "ch61e", "ch62i", "ch62e", "ch63i", "ch63e";
			#mbox-cells = <2>;
			#hwlock-cells = <1>;
			status = "disabled";
		};

		mfis_scp: system-controller@189e1000 {
			compatible = "renesas,r8a78000-mfis-scp";
			reg = <0 0x189e1000 0 0x1000>, <0 0x18840000 0 0x2c000>;
			reg-names = "common", "mboxes";
			interrupts = <GIC_ESPI 296 IRQ_TYPE_LEVEL_HIGH>, <GIC_ESPI 297 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_ESPI 298 IRQ_TYPE_LEVEL_HIGH>, <GIC_ESPI 299 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_ESPI 300 IRQ_TYPE_LEVEL_HIGH>, <GIC_ESPI 301 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_ESPI 302 IRQ_TYPE_LEVEL_HIGH>, <GIC_ESPI 303 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_ESPI 304 IRQ_TYPE_LEVEL_HIGH>, <GIC_ESPI 305 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_ESPI 306 IRQ_TYPE_LEVEL_HIGH>, <GIC_ESPI 307 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_ESPI 308 IRQ_TYPE_LEVEL_HIGH>, <GIC_ESPI 309 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_ESPI 310 IRQ_TYPE_LEVEL_HIGH>, <GIC_ESPI 311 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_ESPI 312 IRQ_TYPE_LEVEL_HIGH>, <GIC_ESPI 313 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_ESPI 314 IRQ_TYPE_LEVEL_HIGH>, <GIC_ESPI 315 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_ESPI 316 IRQ_TYPE_LEVEL_HIGH>, <GIC_ESPI 317 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_ESPI 318 IRQ_TYPE_LEVEL_HIGH>, <GIC_ESPI 319 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_ESPI 320 IRQ_TYPE_LEVEL_HIGH>, <GIC_ESPI 321 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_ESPI 322 IRQ_TYPE_LEVEL_HIGH>, <GIC_ESPI 323 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_ESPI 324 IRQ_TYPE_LEVEL_HIGH>, <GIC_ESPI 325 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_ESPI 326 IRQ_TYPE_LEVEL_HIGH>, <GIC_ESPI 327 IRQ_TYPE_LEVEL_HIGH>;
			/* SCP uses I side IRQ only */
			interrupt-names = "ch0i", "ch1i", "ch2i", "ch3i", "ch4i", "ch5i", "ch6i", "ch7i",
					  "ch8i", "ch9i", "ch10i", "ch11i", "ch12i", "ch13i", "ch14i", "ch15i",
					  "ch16i", "ch17i", "ch18i", "ch19i", "ch20i", "ch21i", "ch22i", "ch23i",
					  "ch24i", "ch25i", "ch26i", "ch27i", "ch28i", "ch29i", "ch30i", "ch31i";
			#mbox-cells = <2>;
			#hwlock-cells = <1>;
			status = "disabled";
		};

		/* Application Processors manage View-1 of a GIC-720AE */
		gic: interrupt-controller@39000000 {
			compatible = "arm,gic-v3";
			#interrupt-cells = <3>;
			#address-cells = <0>;
			interrupt-controller;
			#redistributor-regions = <32>;
			reg = <0x0 0x39000000 0x0 0x10000>,
			      <0x0 0x39080000 0x0 0x40000>,
			      <0x0 0x390c0000 0x0 0x40000>,
			      <0x0 0x39100000 0x0 0x40000>,
			      <0x0 0x39140000 0x0 0x40000>,
			      <0x0 0x39180000 0x0 0x40000>,
			      <0x0 0x391c0000 0x0 0x40000>,
			      <0x0 0x39200000 0x0 0x40000>,
			      <0x0 0x39240000 0x0 0x40000>,
			      <0x0 0x39280000 0x0 0x40000>,
			      <0x0 0x392c0000 0x0 0x40000>,
			      <0x0 0x39300000 0x0 0x40000>,
			      <0x0 0x39340000 0x0 0x40000>,
			      <0x0 0x39380000 0x0 0x40000>,
			      <0x0 0x393c0000 0x0 0x40000>,
			      <0x0 0x39400000 0x0 0x40000>,
			      <0x0 0x39440000 0x0 0x40000>,
			      <0x0 0x39480000 0x0 0x40000>,
			      <0x0 0x394c0000 0x0 0x40000>,
			      <0x0 0x39500000 0x0 0x40000>,
			      <0x0 0x39540000 0x0 0x40000>,
			      <0x0 0x39580000 0x0 0x40000>,
			      <0x0 0x395c0000 0x0 0x40000>,
			      <0x0 0x39600000 0x0 0x40000>,
			      <0x0 0x39640000 0x0 0x40000>,
			      <0x0 0x39680000 0x0 0x40000>,
			      <0x0 0x396c0000 0x0 0x40000>,
			      <0x0 0x39700000 0x0 0x40000>,
			      <0x0 0x39740000 0x0 0x40000>,
			      <0x0 0x39780000 0x0 0x40000>,
			      <0x0 0x397c0000 0x0 0x40000>,
			      <0x0 0x39800000 0x0 0x40000>,
			      <0x0 0x39840000 0x0 0x40000>;
			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
		};

		scif0: serial@c0700000 {
			compatible = "renesas,scif-r8a78000",
				     "renesas,rcar-gen5-scif", "renesas,scif";
			reg = <0 0xc0700000 0 0x40>;
			interrupts = <GIC_ESPI 10 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&dummy_clk_sgasyncd16>, <&dummy_clk_sgasyncd4>, <&scif_clk>;
			clock-names = "fck", "brg_int", "scif_clk";
			status = "disabled";
		};

		scif1: serial@c0704000 {
			compatible = "renesas,scif-r8a78000",
				     "renesas,rcar-gen5-scif", "renesas,scif";
			reg = <0 0xc0704000 0 0x40>;
			interrupts = <GIC_ESPI 11 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&dummy_clk_sgasyncd16>, <&dummy_clk_sgasyncd4>, <&scif_clk>;
			clock-names = "fck", "brg_int", "scif_clk";
			status = "disabled";
		};

		scif3: serial@c0708000 {
			compatible = "renesas,scif-r8a78000",
				     "renesas,rcar-gen5-scif", "renesas,scif";
			reg = <0 0xc0708000 0 0x40>;
			interrupts = <GIC_ESPI 12 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&dummy_clk_sgasyncd16>, <&dummy_clk_sgasyncd4>, <&scif_clk>;
			clock-names = "fck", "brg_int", "scif_clk";
			status = "disabled";
		};

		scif4: serial@c070c000 {
			compatible = "renesas,scif-r8a78000",
				     "renesas,rcar-gen5-scif", "renesas,scif";
			reg = <0 0xc070c000 0 0x40>;
			interrupts = <GIC_ESPI 13 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&dummy_clk_sgasyncd16>, <&dummy_clk_sgasyncd4>, <&scif_clk>;
			clock-names = "fck", "brg_int", "scif_clk";
			status = "disabled";
		};

		hscif0: serial@c0710000 {
			compatible = "renesas,hscif-r8a78000",
				     "renesas,rcar-gen5-hscif", "renesas,hscif";
			reg = <0 0xc0710000 0 0x60>;
			interrupts = <GIC_ESPI 14 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&dummy_clk_sgasyncd4>, <&dummy_clk_sgasyncd4>, <&scif_clk>;
			clock-names = "fck", "brg_int", "scif_clk";
			status = "disabled";
		};

		hscif1: serial@c0714000 {
			compatible = "renesas,hscif-r8a78000",
				     "renesas,rcar-gen5-hscif", "renesas,hscif";
			reg = <0 0xc0714000 0 0x60>;
			interrupts = <GIC_ESPI 15 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&dummy_clk_sgasyncd4>, <&dummy_clk_sgasyncd4>, <&scif_clk>;
			clock-names = "fck", "brg_int", "scif_clk";
			status = "disabled";
		};

		hscif2: serial@c0718000 {
			compatible = "renesas,hscif-r8a78000",
				     "renesas,rcar-gen5-hscif", "renesas,hscif";
			reg = <0 0xc0718000 0 0x60>;
			interrupts = <GIC_ESPI 16 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&dummy_clk_sgasyncd4>, <&dummy_clk_sgasyncd4>, <&scif_clk>;
			clock-names = "fck", "brg_int", "scif_clk";
			status = "disabled";
		};

		hscif3: serial@c071c000 {
			compatible = "renesas,hscif-r8a78000",
				     "renesas,rcar-gen5-hscif", "renesas,hscif";
			reg = <0 0xc071c000 0 0x60>;
			interrupts = <GIC_ESPI 17 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&dummy_clk_sgasyncd4>, <&dummy_clk_sgasyncd4>, <&scif_clk>;
			clock-names = "fck", "brg_int", "scif_clk";
			status = "disabled";
		};

		stcm_transport: sram@c1060000 {
			compatible = "mmio-sram";
			reg = <0x0 0xc1060000 0x0 0x1c00>;
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0 0x0 0xc1060000 0x1c00>;
			/* actual transport nodes must be set per board file */
		};
	};

	timer {
		compatible = "arm,armv8-timer";
		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
			     <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
			     <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
			     <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>,
			     <GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>;
		interrupt-names = "sec-phys", "phys", "virt", "hyp-phys", "hyp-virt";
	};
};