Documentation/devicetree/bindings/clock/apm,xgene-device-clock.yaml

# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/apm,xgene-device-clock.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: APM X-Gene SoC device clocks

maintainers:
  - Khuong Dinh <khuong@os.amperecomputing.com>

properties:
  compatible:
    const: apm,xgene-device-clock

  reg:
    minItems: 1
    maxItems: 2

  reg-names:
    items:
      - enum: [ csr-reg, div-reg ]
      - const: div-reg
    minItems: 1

  clocks:
    maxItems: 1

  "#clock-cells":
    const: 1

  clock-output-names:
    maxItems: 1

  clock-names:
    maxItems: 1

  csr-offset:
    description: Offset to the CSR reset register
    $ref: /schemas/types.yaml#/definitions/uint32
    default: 0

  csr-mask:
    description: CSR reset mask bit
    $ref: /schemas/types.yaml#/definitions/uint32
    default: 0xf

  enable-offset:
    description: Offset to the enable register
    $ref: /schemas/types.yaml#/definitions/uint32
    default: 8

  enable-mask:
    description: CSR enable mask bit
    $ref: /schemas/types.yaml#/definitions/uint32
    default: 0xf

  divider-offset:
    description: Offset to the divider register
    $ref: /schemas/types.yaml#/definitions/uint32
    default: 0

  divider-width:
    description: Width of the divider register
    $ref: /schemas/types.yaml#/definitions/uint32
    default: 0

  divider-shift:
    description: Bit shift of the divider register
    $ref: /schemas/types.yaml#/definitions/uint32
    default: 0

required:
  - compatible
  - reg
  - clocks
  - '#clock-cells'
  - clock-output-names

additionalProperties: false