Documentation/devicetree/bindings/interrupt-controller/arm,gic-v5-iwb.yaml

# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/interrupt-controller/arm,gic-v5-iwb.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: ARM Generic Interrupt Controller, version 5 Interrupt Wire Bridge (IWB)

maintainers:
  - Lorenzo Pieralisi <lpieralisi@kernel.org>
  - Marc Zyngier <maz@kernel.org>

description: |
  The GICv5 architecture defines the guidelines to implement GICv5
  compliant interrupt controllers for AArch64 systems.

  The GICv5 specification can be found at
  https://developer.arm.com/documentation/aes0070

  GICv5 has zero or more Interrupt Wire Bridges (IWB) that are responsible
  for translating wire signals into interrupt messages to the GICv5 ITS.

allOf:
  - $ref: /schemas/interrupt-controller.yaml#

properties:
  compatible:
    const: arm,gic-v5-iwb

  reg:
    items:
      - description: IWB control frame

  "#address-cells":
    const: 0

  "#interrupt-cells":
    description: |
      The 1st cell corresponds to the IWB wire.

      The 2nd cell is the flags, encoded as follows:
      bits[3:0] trigger type and level flags.

      1 = low-to-high edge triggered
      2 = high-to-low edge triggered
      4 = active high level-sensitive
      8 = active low level-sensitive

    const: 2

  interrupt-controller: true

  msi-parent:
    maxItems: 1

required:
  - compatible
  - reg
  - "#interrupt-cells"
  - interrupt-controller
  - msi-parent

additionalProperties: false

examples:
  - |
    interrupt-controller@2f000000 {
      compatible = "arm,gic-v5-iwb";
      reg = <0x2f000000 0x10000>;

      #address-cells = <0>;

      #interrupt-cells = <2>;
      interrupt-controller;

      msi-parent = <&its0 64>;
    };
...