Documentation/devicetree/bindings/net/altr,socfpga-stmmac.yaml

# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/net/altr,socfpga-stmmac.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Altera SOCFPGA SoC DWMAC controller

maintainers:
  - Matthew Gerlach <matthew.gerlach@altera.com>

description:
  This binding describes the Altera SOCFPGA SoC implementation of the
  Synopsys DWMAC for the Cyclone5, Arria5, Stratix10, Agilex5 and Agilex7
  families of chips.
  # TODO: Determine how to handle the Arria10 reset-name, stmmaceth-ocp, that
  # does not validate against net/snps,dwmac.yaml.

select:
  properties:
    compatible:
      contains:
        enum:
          - altr,socfpga-stmmac
          - altr,socfpga-stmmac-a10-s10
          - altr,socfpga-stmmac-agilex5

  required:
    - compatible

properties:
  compatible:
    oneOf:
      - items:
          - const: altr,socfpga-stmmac
          - const: snps,dwmac-3.70a
          - const: snps,dwmac
      - items:
          - const: altr,socfpga-stmmac-a10-s10
          - const: snps,dwmac-3.72a
          - const: snps,dwmac
      - items:
          - const: altr,socfpga-stmmac-a10-s10
          - const: snps,dwmac-3.74a
          - const: snps,dwmac
      - items:
          - const: altr,socfpga-stmmac-agilex5
          - const: snps,dwxgmac-2.10

  clocks:
    minItems: 1
    items:
      - description: GMAC main clock
      - description:
          PTP reference clock. This clock is used for programming the
          Timestamp Addend Register. If not passed then the system
          clock will be used and this is fine on some platforms.

  clock-names:
    minItems: 1
    items:
      - const: stmmaceth
      - const: ptp_ref

  interrupts:
    maxItems: 1

  interrupt-names:
    items:
      - const: macirq

  iommus:
    minItems: 1
    maxItems: 2

  phy-mode:
    enum:
      - gmii
      - mii
      - rgmii
      - rgmii-id
      - rgmii-rxid
      - rgmii-txid
      - sgmii
      - 1000base-x

  rxc-skew-ps:
    description: Skew control of RXC pad

  rxd0-skew-ps:
    description: Skew control of RX data 0 pad

  rxd1-skew-ps:
    description: Skew control of RX data 1 pad

  rxd2-skew-ps:
    description: Skew control of RX data 2 pad

  rxd3-skew-ps:
    description: Skew control of RX data 3 pad

  rxdv-skew-ps:
    description: Skew control of RX CTL pad

  txc-skew-ps:
    description: Skew control of TXC pad

  txen-skew-ps:
    description: Skew control of TXC pad

  altr,emac-splitter:
    $ref: /schemas/types.yaml#/definitions/phandle
    description:
      Should be the phandle to the emac splitter soft IP node if DWMAC
      controller is connected an emac splitter.

  altr,f2h_ptp_ref_clk:
    $ref: /schemas/types.yaml#/definitions/phandle
    description:
      Phandle to Precision Time Protocol reference clock. This clock is
      common to gmac instances and defaults to osc1.

  altr,gmii-to-sgmii-converter:
    $ref: /schemas/types.yaml#/definitions/phandle
    description:
      Should be the phandle to the gmii to sgmii converter soft IP.

  altr,sysmgr-syscon:
    $ref: /schemas/types.yaml#/definitions/phandle-array
    description:
      Should be the phandle to the system manager node that encompass
      the glue register, the register offset, and the register shift.
      On Cyclone5/Arria5, the register shift represents the PHY mode
      bits, while on the Arria10/Stratix10/Agilex platforms, the
      register shift represents bit for each emac to enable/disable
      signals from the FPGA fabric to the EMAC modules.
    items:
      - items:
          - description: phandle to the system manager node
          - description: offset of the control register
          - description: shift within the control register

patternProperties:
  "^mdio[0-9]$":
    type: object

required:
  - compatible
  - clocks
  - clock-names
  - altr,sysmgr-syscon

allOf:
  - $ref: snps,dwmac.yaml#

unevaluatedProperties: false

examples:

  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/interrupt-controller/irq.h>
    soc {
        #address-cells = <1>;
        #size-cells = <1>;
        ethernet@ff700000 {
            compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a",
            "snps,dwmac";
            altr,sysmgr-syscon = <&sysmgr 0x60 0>;
            reg = <0xff700000 0x2000>;
            interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
            interrupt-names = "macirq";
            mac-address = [00 00 00 00 00 00]; /* Filled in by U-Boot */
            clocks = <&emac_0_clk>;
            clock-names = "stmmaceth";
            phy-mode = "sgmii";
        };
    };