Documentation/devicetree/bindings/net/dsa/micrel,ks8995.yaml

# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/net/dsa/micrel,ks8995.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Micrel KS8995 Family DSA Switches

maintainers:
  - Linus Walleij <linusw@kernel.org>

description:
  The Micrel KS8995 DSA Switches are 100 Mbit switches that were produced in
  the early-to-mid 2000s. The chip features a CPU port and four outgoing ports,
  each with an internal PHY. The chip itself is managed over SPI, but all the
  PHYs need to be accessed from an external MDIO channel.

  Further, a fifth PHY is available and can be used separately from the switch
  fabric, connected to an external MII interface name MII-P5. This is
  unrelated from the CPU-facing port 5 which is used for DSA MII traffic.

properties:
  compatible:
    enum:
      - micrel,ks8995
      - micrel,ksz8795
      - micrel,ksz8864

  reg:
    maxItems: 1

  reset-gpios:
    description: GPIO to be used to reset the whole device
    maxItems: 1

allOf:
  - $ref: dsa.yaml#/$defs/ethernet-ports
  - $ref: /schemas/spi/spi-peripheral-props.yaml#

required:
  - compatible
  - reg

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/gpio/gpio.h>

    spi {
      #address-cells = <1>;
      #size-cells = <0>;

      ethernet-switch@0 {
        compatible = "micrel,ks8995";
        reg = <0>;
        spi-max-frequency = <25000000>;

        ethernet-ports {
          #address-cells = <1>;
          #size-cells = <0>;

          ethernet-port@0 {
            reg = <0>;
            label = "lan1";
          };
          ethernet-port@1 {
            reg = <1>;
            label = "lan2";
          };
          ethernet-port@2 {
            reg = <2>;
            label = "lan3";
          };
          ethernet-port@3 {
            reg = <3>;
            label = "lan4";
          };
          ethernet-port@4 {
            reg = <4>;
            ethernet = <&mac2>;
            phy-mode = "mii";
            fixed-link {
              speed = <100>;
              full-duplex;
            };
          };
        };
      };
    };

    soc {
      #address-cells = <1>;
      #size-cells = <1>;

      /* The WAN port connected on MII-P5 */
      ethernet-port@1000 {
        reg = <0x00001000 0x1000>;
        label = "wan";
        phy-mode = "mii";
        phy-handle = <&phy5>;
      };

      mac2: ethernet-port@2000 {
        reg = <0x00002000 0x1000>;
        phy-mode = "mii";
        fixed-link {
          speed = <100>;
          full-duplex;
        };
      };
    };

    mdio {
      #address-cells = <1>;
      #size-cells = <0>;

      /* LAN PHYs 1-4 accessible over external MDIO */
      phy1: ethernet-phy@1 {
        reg = <1>;
      };
      phy2: ethernet-phy@2 {
        reg = <2>;
      };
      phy3: ethernet-phy@3 {
        reg = <3>;
      };
      phy4: ethernet-phy@4 {
        reg = <4>;
      };
      /* WAN PHY accessible over external MDIO */
      phy5: ethernet-phy@5 {
        reg = <5>;
      };
    };