| .. SPDX-License-Identifier: GPL-2.0 |
| |
| ================================ |
| CEDT - CXL Early Discovery Table |
| ================================ |
| |
| The CXL Early Discovery Table is generated by BIOS to describe the CXL memory |
| regions configured at boot by the BIOS. |
| |
| CHBS |
| ==== |
| The CXL Host Bridge Structure describes CXL host bridges. Other than describing |
| device register information, it reports the specific host bridge UID for this |
| host bridge. These host bridge ID's will be referenced in other tables. |
| |
| Example :: |
| |
| Subtable Type : 00 [CXL Host Bridge Structure] |
| Reserved : 00 |
| Length : 0020 |
| Associated host bridge : 00000007 <- Host bridge _UID |
| Specification version : 00000001 |
| Reserved : 00000000 |
| Register base : 0000010370400000 |
| Register length : 0000000000010000 |
| |
| CFMWS |
| ===== |
| The CXL Fixed Memory Window structure describes a memory region associated |
| with one or more CXL host bridges (as described by the CHBS). It additionally |
| describes any inter-host-bridge interleave configuration that may have been |
| programmed by BIOS. |
| |
| Example :: |
| |
| Subtable Type : 01 [CXL Fixed Memory Window Structure] |
| Reserved : 00 |
| Length : 002C |
| Reserved : 00000000 |
| Window base address : 000000C050000000 <- Memory Region |
| Window size : 0000003CA0000000 |
| Interleave Members (2^n) : 01 <- Interleave configuration |
| Interleave Arithmetic : 00 |
| Reserved : 0000 |
| Granularity : 00000000 |
| Restrictions : 0006 |
| QtgId : 0001 |
| First Target : 00000007 <- Host Bridge _UID |
| Next Target : 00000006 <- Host Bridge _UID |
| |
| The restriction field dictates what this SPA range may be used for (memory type, |
| voltile vs persistent, etc). One or more bits may be set. :: |
| |
| Bit[0]: CXL Type 2 Memory |
| Bit[1]: CXL Type 3 Memory |
| Bit[2]: Volatile Memory |
| Bit[3]: Persistent Memory |
| Bit[4]: Fixed Config (HPA cannot be re-used) |
| |
| INTRA-host-bridge interleave (multiple devices on one host bridge) is NOT |
| reported in this structure, and is solely defined via CXL device decoder |
| programming (host bridge and endpoint decoders). |
