drivers/gpu/drm/msm/registers/display/mdss.xml

<?xml version="1.0" encoding="UTF-8"?>
<database xmlns="http://nouveau.freedesktop.org/"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd">
<import file="freedreno_copyright.xml"/>

<domain name="MDSS" width="32">
	<reg32 offset="0x00000" name="HW_VERSION">
		<bitfield name="STEP" low="0" high="15" type="uint"/>
		<bitfield name="MINOR" low="16" high="27" type="uint"/>
		<bitfield name="MAJOR" low="28" high="31" type="uint"/>
	</reg32>

	<reg32 offset="0x00010" name="HW_INTR_STATUS">
		<bitfield name="INTR_MDP"  pos="0"  type="boolean"/>
		<bitfield name="INTR_DSI0" pos="4"  type="boolean"/>
		<bitfield name="INTR_DSI1" pos="5"  type="boolean"/>
		<bitfield name="INTR_HDMI" pos="8"  type="boolean"/>
		<bitfield name="INTR_EDP"  pos="12" type="boolean"/>
	</reg32>

	<reg32 offset="0x00058" name="UBWC_DEC_HW_VERSION"/>

	<reg32 offset="0x00144" name="UBWC_STATIC">
		<bitfield name="UBWC_SWIZZLE" low="0" high="2"/>
		<bitfield name="UBWC_BANK_SPREAD" pos="3"/>
		<!-- high=5 for UBWC < 4.0 -->
		<bitfield name="HIGHEST_BANK_BIT" low="4" high="6"/>
		<bitfield name="UBWC_MIN_ACC_LEN" low="8" high="9"/>
		<bitfield name="UBWC_AMSBC" pos="10"/>
		<bitfield name="MACROTILE_MODE" pos="12"/>
	</reg32>

	<reg32 offset="0x00150" name="UBWC_CTRL_2"/>
	<reg32 offset="0x00154" name="UBWC_PREDICTION_MODE"/>
</domain>

</database>