Documentation/devicetree/bindings/pci/andestech,qilai-pcie.yaml

# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pci/andestech,qilai-pcie.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Andes QiLai PCIe host controller

description:
  Andes QiLai PCIe host controller is based on the Synopsys DesignWare
  PCI core.

maintainers:
  - Randolph Lin <randolph@andestech.com>

allOf:
  - $ref: /schemas/pci/snps,dw-pcie.yaml#

properties:
  compatible:
    const: andestech,qilai-pcie

  reg:
    items:
      - description: Data Bus Interface (DBI) registers.
      - description: APB registers.
      - description: PCIe configuration space region.

  reg-names:
    items:
      - const: dbi
      - const: apb
      - const: config

  dma-coherent: true

  ranges:
    maxItems: 2

  interrupts:
    maxItems: 1

  interrupt-names:
    items:
      - const: msi

required:
  - reg
  - reg-names
  - interrupts
  - interrupt-names

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/irq.h>

    soc {
      #address-cells = <2>;
      #size-cells = <2>;

      pcie@80000000 {
        compatible = "andestech,qilai-pcie";
        device_type = "pci";
        reg = <0x0 0x80000000 0x0 0x20000000>,
              <0x0 0x04000000 0x0 0x00001000>,
              <0x0 0x00000000 0x0 0x00010000>;
        reg-names = "dbi", "apb", "config";
        dma-coherent;

        linux,pci-domain = <0>;
        #address-cells = <3>;
        #size-cells = <2>;
        ranges = <0x02000000 0x00 0x10000000 0x00 0x10000000 0x00 0xf0000000>,
                 <0x43000000 0x01 0x00000000 0x01 0x00000000 0x02 0x00000000>;

        #interrupt-cells = <1>;
        interrupts = <0xf>;
        interrupt-names = "msi";
        interrupt-parent = <&plic0>;
        interrupt-map-mask = <0 0 0 0>;
        interrupt-map = <0 0 0 1 &plic0 0xf IRQ_TYPE_LEVEL_HIGH>,
                        <0 0 0 2 &plic0 0xf IRQ_TYPE_LEVEL_HIGH>,
                        <0 0 0 3 &plic0 0xf IRQ_TYPE_LEVEL_HIGH>,
                        <0 0 0 4 &plic0 0xf IRQ_TYPE_LEVEL_HIGH>;
      };
    };
...