Documentation/devicetree/bindings/pci/sophgo,sg2044-pcie.yaml

# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pci/sophgo,sg2044-pcie.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: DesignWare based PCIe Root Complex controller on Sophgo SoCs

maintainers:
  - Inochi Amaoto <inochiama@gmail.com>

description:
  SG2044 SoC PCIe Root Complex controller is based on the Synopsys DesignWare
  PCIe IP and thus inherits all the common properties defined in
  snps,dw-pcie.yaml.

allOf:
  - $ref: /schemas/pci/pci-host-bridge.yaml#
  - $ref: /schemas/pci/snps,dw-pcie.yaml#

properties:
  compatible:
    const: sophgo,sg2044-pcie

  reg:
    items:
      - description: Data Bus Interface (DBI) registers
      - description: iATU registers
      - description: Config registers
      - description: Sophgo designed configuration registers

  reg-names:
    items:
      - const: dbi
      - const: atu
      - const: config
      - const: app

  clocks:
    items:
      - description: core clk

  clock-names:
    items:
      - const: core

  interrupt-controller:
    description: Interrupt controller node for handling legacy PCI interrupts.
    type: object

    properties:
      "#address-cells":
        const: 0

      "#interrupt-cells":
        const: 1

      interrupt-controller: true

      interrupts:
        items:
          - description: combined legacy interrupt

    required:
      - "#address-cells"
      - "#interrupt-cells"
      - interrupt-controller
      - interrupts

    additionalProperties: false

  msi-parent: true

  ranges:
    maxItems: 5

required:
  - compatible
  - reg
  - clocks

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/irq.h>

    soc {
      #address-cells = <2>;
      #size-cells = <2>;

      pcie@6c00400000 {
        compatible = "sophgo,sg2044-pcie";
        reg = <0x6c 0x00400000 0x0 0x00001000>,
              <0x6c 0x00700000 0x0 0x00004000>,
              <0x40 0x00000000 0x0 0x00001000>,
              <0x6c 0x00780c00 0x0 0x00000400>;
        reg-names = "dbi", "atu", "config", "app";
        #address-cells = <3>;
        #size-cells = <2>;
        bus-range = <0x00 0xff>;
        clocks = <&clk 0>;
        clock-names = "core";
        device_type = "pci";
        linux,pci-domain = <0>;
        msi-parent = <&msi>;
        ranges = <0x01000000 0x0  0x00000000  0x40 0x10000000  0x0 0x00200000>,
                 <0x42000000 0x0  0x00000000  0x0  0x00000000  0x0 0x04000000>,
                 <0x02000000 0x0  0x04000000  0x0  0x04000000  0x0 0x04000000>,
                 <0x43000000 0x42 0x00000000  0x42 0x00000000  0x2 0x00000000>,
                 <0x03000000 0x41 0x00000000  0x41 0x00000000  0x1 0x00000000>;

        interrupt-controller {
          #address-cells = <0>;
          #interrupt-cells = <1>;
          interrupt-controller;
          interrupt-parent = <&intc>;
          interrupts = <64 IRQ_TYPE_LEVEL_HIGH>;
        };
      };
    };
...