arch/arm64/boot/dts/exynos/axis/artpec8.dtsi

// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
 * Axis ARTPEC-8 SoC device tree source
 *
 * Copyright (c) 2025 Samsung Electronics Co., Ltd.
 *             https://www.samsung.com
 * Copyright (c) 2025  Axis Communications AB.
 *             https://www.axis.com
 */

#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/axis,artpec8-clk.h>

/ {
	compatible = "axis,artpec8";
	interrupt-parent = <&gic>;
	#address-cells = <2>;
	#size-cells = <2>;

	aliases {
		pinctrl0 = &pinctrl_fsys;
		pinctrl1 = &pinctrl_peric;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu0: cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <0x0>;
			enable-method = "psci";
			cpu-idle-states = <&cpu_sleep>;
			clocks = <&cmu_cpucl CLK_GOUT_CPUCL_CLUSTER_CPU>;
			clock-names = "cpu";
		};

		cpu1: cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <0x1>;
			enable-method = "psci";
			cpu-idle-states = <&cpu_sleep>;
		};

		cpu2: cpu@2 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <0x2>;
			enable-method = "psci";
			cpu-idle-states = <&cpu_sleep>;
		};

		cpu3: cpu@3 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <0x3>;
			enable-method = "psci";
			cpu-idle-states = <&cpu_sleep>;
		};

		idle-states {
			entry-method = "psci";

			cpu_sleep: cpu-sleep {
				compatible = "arm,idle-state";
				arm,psci-suspend-param = <0x0010000>;
				local-timer-stop;
				entry-latency-us = <300>;
				exit-latency-us = <1200>;
				min-residency-us = <2000>;
			};
		};
	};

	fin_pll: clock-finpll {
		compatible = "fixed-factor-clock";
		clocks = <&osc_clk>;
		#clock-cells = <0>;
		clock-div = <2>;
		clock-mult = <1>;
		clock-output-names = "fin_pll";
	};

	osc_clk: clock-osc {
		/* XXTI */
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-output-names = "osc_clk";
	};

	pmu {
		compatible = "arm,cortex-a53-pmu";
		interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
	};

	psci {
		compatible = "arm,psci-0.2";
		method = "smc";
	};

	soc: soc@0 {
		compatible = "simple-bus";
		ranges = <0x0 0x0 0x0 0x17000000>;
		#address-cells = <1>;
		#size-cells = <1>;

		cmu_imem: clock-controller@10010000 {
			compatible = "axis,artpec8-cmu-imem";
			reg = <0x10010000 0x4000>;
			#clock-cells = <1>;
			clocks = <&fin_pll>,
				 <&cmu_cmu CLK_DOUT_CMU_IMEM_ACLK>,
				 <&cmu_cmu CLK_DOUT_CMU_IMEM_JPEG>;
			clock-names = "fin_pll", "aclk", "jpeg";
		};

		timer@10040000 {
			compatible = "axis,artpec8-mct", "samsung,exynos4210-mct";
			reg = <0x10040000 0x1000>;
			clocks = <&fin_pll>, <&cmu_imem CLK_GOUT_IMEM_MCT_PCLK>;
			clock-names = "fin_pll", "mct";
			interrupts = <GIC_SPI 455 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 456 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 457 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 459 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 460 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 463 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>;
		};

		gic: interrupt-controller@10201000 {
			compatible = "arm,gic-400";
			reg = <0x10201000 0x1000>,
			      <0x10202000 0x2000>,
			      <0x10204000 0x2000>,
			      <0x10206000 0x2000>;
			#interrupt-cells = <3>;
			interrupt-controller;
			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
		};

		cmu_cpucl: clock-controller@11410000 {
			compatible = "axis,artpec8-cmu-cpucl";
			reg = <0x11410000 0x4000>;
			#clock-cells = <1>;
			clocks = <&fin_pll>,
				 <&cmu_cmu CLK_DOUT_CMU_CPUCL_SWITCH>;
			clock-names = "fin_pll", "switch";
		};

		cmu_cmu: clock-controller@12400000 {
			compatible = "axis,artpec8-cmu-cmu";
			reg = <0x12400000 0x4000>;
			#clock-cells = <1>;
			clocks = <&fin_pll>;
			clock-names = "fin_pll";
		};

		cmu_core: clock-controller@12410000 {
			compatible = "axis,artpec8-cmu-core";
			reg = <0x12410000 0x4000>;
			#clock-cells = <1>;
			clocks = <&fin_pll>,
				 <&cmu_cmu CLK_DOUT_CMU_CORE_MAIN>,
				 <&cmu_cmu CLK_DOUT_CMU_CORE_DLP>;
			clock-names = "fin_pll", "main", "dlp";
		};

		cmu_bus: clock-controller@12c10000 {
			compatible = "axis,artpec8-cmu-bus";
			reg = <0x12c10000 0x4000>;
			#clock-cells = <1>;
			clocks = <&fin_pll>,
				 <&cmu_cmu CLK_DOUT_CMU_BUS>,
				 <&cmu_cmu CLK_DOUT_CMU_BUS_DLP>;
			clock-names = "fin_pll", "bus", "dlp";
		};

		cmu_peri: clock-controller@16410000 {
			compatible = "axis,artpec8-cmu-peri";
			reg = <0x16410000 0x4000>;
			#clock-cells = <1>;
			clocks = <&fin_pll>,
				 <&cmu_cmu CLK_DOUT_CMU_PERI_IP>,
				 <&cmu_cmu CLK_DOUT_CMU_PERI_AUDIO>,
				 <&cmu_cmu CLK_DOUT_CMU_PERI_DISP>;
			clock-names = "fin_pll", "ip", "audio", "disp";
		};

		pinctrl_peric: pinctrl@165f0000 {
			compatible = "axis,artpec8-pinctrl";
			reg = <0x165f0000 0x1000>;
			interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
		};

		cmu_fsys: clock-controller@16c10000 {
			compatible = "axis,artpec8-cmu-fsys";
			reg = <0x16c10000 0x4000>;
			#clock-cells = <1>;
			clocks = <&fin_pll>,
				 <&cmu_cmu CLK_DOUT_CMU_FSYS_SCAN0>,
				 <&cmu_cmu CLK_DOUT_CMU_FSYS_SCAN1>,
				 <&cmu_cmu CLK_DOUT_CMU_FSYS_BUS>,
				 <&cmu_cmu CLK_DOUT_CMU_FSYS_IP>;
			clock-names = "fin_pll", "scan0", "scan1", "bus", "ip";
		};

		pinctrl_fsys: pinctrl@16c30000 {
			compatible = "axis,artpec8-pinctrl";
			reg = <0x16c30000 0x1000>;
			interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
		};

		serial_0: serial@16cc0000 {
			compatible = "axis,artpec8-uart";
			reg = <0x16cc0000 0x100>;
			clocks = <&cmu_fsys CLK_GOUT_FSYS_UART0_PCLK>,
				 <&cmu_fsys CLK_GOUT_FSYS_UART0_SCLK_UART>;
			clock-names = "uart", "clk_uart_baud0";
			interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
			pinctrl-names = "default";
			pinctrl-0 = <&serial0_bus>;
		};
	};

	timer {
		compatible = "arm,armv8-timer";
		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
	};
};