arch/arm64/boot/dts/freescale/imx8qm-tqma8qm.dtsi - linux - Git at Google

 // SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
 /*
  * Copyright (c) 2019-2026 TQ-Systems GmbH <linux@ew.tq-group.com>,
  * D-82229 Seefeld, Germany.
  * Author: Alexander Stein
  */

 #include <dt-bindings/firmware/imx/rsrc.h>
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/thermal/thermal.h>

 #include "imx8qm.dtsi"

 / {
 	model = "TQ-Systems i.MX8QM TQMa8QM";
 	compatible = "tq,imx8qm-tqma8qm", "fsl,imx8qm";

 	/* Due to missing workaround for ERR050104 */
 	cpus {
 		/delete-node/ cpu-map;
 		/delete-node/ cpu@100;
 		/delete-node/ cpu@101;
 	};

 	memory@80000000 {
 		device_type = "memory";
 		/*
 		 * DRAM base addr, size : 1024 MiB DRAM
 		 * should be corrected by bootloader
 		 */
 		reg = <0x00000000 0x80000000 0 0x40000000>;
 	};

 	reg_tqma8x_v3v3: regulator-tqma8x-v3v3 {
 		compatible = "regulator-fixed";
 		regulator-name = "V_3V3";
 		regulator-min-microvolt = <3300000>;
 		regulator-max-microvolt = <3300000>;
 		regulator-always-on;
 	};

 	/* SW7 controlled by SCU */
 	reg_1v8_io1: regulator-v1v8-io1 {
 		compatible = "regulator-fixed";
 		regulator-name = "V_1V8_IO1";
 		regulator-min-microvolt = <1800000>;
 		regulator-max-microvolt = <1800000>;
 		regulator-always-on;
 	};

 	/* LDO4 controlled by SCU */
 	reg_3v3_emmc: regulator-v3v3-emmc {
 		compatible = "regulator-fixed";
 		regulator-name = "V_3V3_EMMC";
 		regulator-min-microvolt = <3300000>;
 		regulator-max-microvolt = <3300000>;
 		regulator-always-on;
 	};
 };

 &acm {
 	status = "okay";
 };

 &adc0 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_adc0>;
 	vref-supply = <&reg_vref_v1v8>;
 	status = "okay";
 };

 /* TQMa8QM only uses industrial grade, reduce trip points accordingly */
 &cpu_alert0 {
 	temperature = <95000>;
 };

 &cpu_crit0 {
 	temperature = <100000>;
 };

 &cpu_alert1 {
 	temperature = <95000>;
 };

 &cpu_crit1 {
 	temperature = <100000>;
 };

 &gpu_alert0 {
 	temperature = <95000>;
 };

 &gpu_crit0 {
 	temperature = <100000>;
 };

 &gpu_alert1 {
 	temperature = <95000>;
 };

 &gpu_crit1 {
 	temperature = <100000>;
 };

 &drc_alert0 {
 	temperature = <95000>;
 };

 &drc_crit0 {
 	temperature = <100000>;
 };
 /* end of temperature grade adjustments */

 &flexspi0 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_flexspi0>;
 	status = "okay";

 	flash0: flash@0 {
 		compatible = "jedec,spi-nor";
 		reg = <0>;
 		spi-max-frequency = <66000000>;
 		spi-tx-bus-width = <4>;
 		spi-rx-bus-width = <4>;
 		vcc-supply = <&reg_1v8_io1>;

 		partitions {
 			compatible = "fixed-partitions";
 			#address-cells = <1>;
 			#size-cells = <1>;
 		};
 	};
 };

 &i2c1 {
 	clock-frequency = <400000>;
 	pinctrl-names = "default", "gpio";
 	pinctrl-0 = <&pinctrl_lpi2c1>;
 	pinctrl-1 = <&pinctrl_lpi2c1gpio>;
 	scl-gpios = <&lsio_gpio0 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
 	sda-gpios = <&lsio_gpio0 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
 	status = "okay";

 	se97: temperature-sensor@1b {
 		compatible = "nxp,se97b", "jedec,jc-42.4-temp";
 		reg = <0x1b>;
 	};

 	pcf85063: rtc@51 {
 		compatible = "nxp,pcf85063a";
 		reg = <0x51>;
 		quartz-load-femtofarads = <7000>;
 	};

 	at24c02: eeprom@53 {
 		compatible = "nxp,se97b", "atmel,24c02";
 		reg = <0x53>;
 		pagesize = <16>;
 		read-only;
 		vcc-supply = <&reg_tqma8x_v3v3>;
 	};

 	m24c64: eeprom@57 {
 		compatible = "atmel,24c64";
 		reg = <0x57>;
 		pagesize = <32>;
 		vcc-supply = <&reg_tqma8x_v3v3>;
 	};
 };

 &mu_m0 {
 	status = "okay";
 };

 &mu1_m0 {
 	status = "okay";
 };

 &mu2_m0 {
 	status = "okay";
 };

 &thermal_zones {
 	/delete-node/ cpu1-thermal;

 	pmic0-thermal {
 		polling-delay-passive = <250>;
 		polling-delay = <2000>;
 		thermal-sensors = <&tsens IMX_SC_R_PMIC_0>;

 		trips {
 			pmic_alert0: trip0 {
 				temperature = <110000>;
 				hysteresis = <2000>;
 				type = "passive";
 			};
 			pmic_crit0: trip1 {
 				temperature = <125000>;
 				hysteresis = <2000>;
 				type = "critical";
 			};
 		};

 		cooling-maps {
 			map0 {
 				trip = <&pmic_alert0>;
 				cooling-device =
 					<&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 					<&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 					<&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 					<&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 			};
 		};
 	};
 };

 &usdhc1 {
 	pinctrl-names = "default", "state_100mhz", "state_200mhz";
 	pinctrl-0 = <&pinctrl_usdhc1>;
 	pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
 	pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
 	bus-width = <8>;
 	vmmc-supply = <&reg_3v3_emmc>;
 	vqmmc-supply = <&reg_1v8_io1>;
 	no-sd;
 	no-sdio;
 	non-removable;
 	status = "okay";
 };

 &vpu {
 	compatible = "nxp,imx8qm-vpu";
 	status = "okay";
 };

 &vpu_core0 {
 	memory-region = <&decoder_boot>, <&decoder_rpc>;
 	status = "okay";
 };

 &vpu_core1 {
 	memory-region = <&encoder1_boot>, <&encoder1_rpc>;
 	status = "okay";
 };

 &vpu_core2 {
 	memory-region = <&encoder2_boot>, <&encoder2_rpc>;
 	status = "okay";
 };

 &iomuxc {
 	pinctrl_lpi2c1: lpi2c1grp {
 		fsl,pins = <IMX8QM_GPT0_CAPTURE_DMA_I2C1_SDA		0x0600004d>,
 			   <IMX8QM_GPT0_CLK_DMA_I2C1_SCL		0x0600004d>;
 	};

 	pinctrl_lpi2c1gpio: lpi2c1gpiogrp {
 		fsl,pins = <IMX8QM_GPT0_CAPTURE_LSIO_GPIO0_IO15		0x0600004d>,
 			   <IMX8QM_GPT0_CLK_LSIO_GPIO0_IO14		0x0600004d>;
 	};

 	pinctrl_usdhc1: usdhc1grp {
 		fsl,pins = <IMX8QM_EMMC0_CLK_CONN_EMMC0_CLK		0x06000041>,
 			   <IMX8QM_EMMC0_CMD_CONN_EMMC0_CMD		0x00000021>,
 			   <IMX8QM_EMMC0_DATA0_CONN_EMMC0_DATA0		0x00000021>,
 			   <IMX8QM_EMMC0_DATA1_CONN_EMMC0_DATA1		0x00000021>,
 			   <IMX8QM_EMMC0_DATA2_CONN_EMMC0_DATA2		0x00000021>,
 			   <IMX8QM_EMMC0_DATA3_CONN_EMMC0_DATA3		0x00000021>,
 			   <IMX8QM_EMMC0_DATA4_CONN_EMMC0_DATA4		0x00000021>,
 			   <IMX8QM_EMMC0_DATA5_CONN_EMMC0_DATA5		0x00000021>,
 			   <IMX8QM_EMMC0_DATA6_CONN_EMMC0_DATA6		0x00000021>,
 			   <IMX8QM_EMMC0_DATA7_CONN_EMMC0_DATA7		0x00000021>,
 			   <IMX8QM_EMMC0_STROBE_CONN_EMMC0_STROBE	0x00000041>,
 			   <IMX8QM_EMMC0_RESET_B_CONN_EMMC0_RESET_B	0x00000021>;
 	};

 	pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
 		fsl,pins = <IMX8QM_EMMC0_CLK_CONN_EMMC0_CLK		0x06000040>,
 			   <IMX8QM_EMMC0_CMD_CONN_EMMC0_CMD		0x00000021>,
 			   <IMX8QM_EMMC0_DATA0_CONN_EMMC0_DATA0		0x00000021>,
 			   <IMX8QM_EMMC0_DATA1_CONN_EMMC0_DATA1		0x00000021>,
 			   <IMX8QM_EMMC0_DATA2_CONN_EMMC0_DATA2		0x00000021>,
 			   <IMX8QM_EMMC0_DATA3_CONN_EMMC0_DATA3		0x00000021>,
 			   <IMX8QM_EMMC0_DATA4_CONN_EMMC0_DATA4		0x00000021>,
 			   <IMX8QM_EMMC0_DATA5_CONN_EMMC0_DATA5		0x00000021>,
 			   <IMX8QM_EMMC0_DATA6_CONN_EMMC0_DATA6		0x00000021>,
 			   <IMX8QM_EMMC0_DATA7_CONN_EMMC0_DATA7		0x00000021>,
 			   <IMX8QM_EMMC0_STROBE_CONN_EMMC0_STROBE	0x00000041>,
 			   <IMX8QM_EMMC0_RESET_B_CONN_EMMC0_RESET_B	0x00000021>;
 	};

 	pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
 		fsl,pins = <IMX8QM_EMMC0_CLK_CONN_EMMC0_CLK		0x06000040>,
 			   <IMX8QM_EMMC0_CMD_CONN_EMMC0_CMD		0x00000021>,
 			   <IMX8QM_EMMC0_DATA0_CONN_EMMC0_DATA0		0x00000021>,
 			   <IMX8QM_EMMC0_DATA1_CONN_EMMC0_DATA1		0x00000021>,
 			   <IMX8QM_EMMC0_DATA2_CONN_EMMC0_DATA2		0x00000021>,
 			   <IMX8QM_EMMC0_DATA3_CONN_EMMC0_DATA3		0x00000021>,
 			   <IMX8QM_EMMC0_DATA4_CONN_EMMC0_DATA4		0x00000021>,
 			   <IMX8QM_EMMC0_DATA5_CONN_EMMC0_DATA5		0x00000021>,
 			   <IMX8QM_EMMC0_DATA6_CONN_EMMC0_DATA6		0x00000021>,
 			   <IMX8QM_EMMC0_DATA7_CONN_EMMC0_DATA7		0x00000021>,
 			   <IMX8QM_EMMC0_STROBE_CONN_EMMC0_STROBE	0x00000041>,
 			   <IMX8QM_EMMC0_RESET_B_CONN_EMMC0_RESET_B	0x00000021>;
 	};

 	pinctrl_flexspi0: flexspi0grp {
 		fsl,pins = <IMX8QM_QSPI0A_DATA0_LSIO_QSPI0A_DATA0	0x0000004d>,
 			   <IMX8QM_QSPI0A_DATA1_LSIO_QSPI0A_DATA1	0x0000004d>,
 			   <IMX8QM_QSPI0A_DATA2_LSIO_QSPI0A_DATA2	0x0000004d>,
 			   <IMX8QM_QSPI0A_DATA3_LSIO_QSPI0A_DATA3	0x0000004d>,
 			   <IMX8QM_QSPI0A_DQS_LSIO_QSPI0A_DQS		0x0000004d>,
 			   <IMX8QM_QSPI0A_SS0_B_LSIO_QSPI0A_SS0_B	0x0000004d>,
 			   <IMX8QM_QSPI0A_SS1_B_LSIO_QSPI0A_SS1_B	0x0000004d>,
 			   <IMX8QM_QSPI0A_SCLK_LSIO_QSPI0A_SCLK		0x0000004d>,
 			   <IMX8QM_QSPI0B_SCLK_LSIO_QSPI0B_SCLK		0x0000004d>,
 			   <IMX8QM_QSPI0B_DATA0_LSIO_QSPI0B_DATA0	0x0000004d>,
 			   <IMX8QM_QSPI0B_DATA1_LSIO_QSPI0B_DATA1	0x0000004d>,
 			   <IMX8QM_QSPI0B_DATA2_LSIO_QSPI0B_DATA2	0x0000004d>,
 			   <IMX8QM_QSPI0B_DATA3_LSIO_QSPI0B_DATA3	0x0000004d>,
 			   <IMX8QM_QSPI0B_DQS_LSIO_QSPI0B_DQS		0x0000004d>,
 			   <IMX8QM_QSPI0B_SS0_B_LSIO_QSPI0B_SS0_B	0x0000004d>,
 			   <IMX8QM_QSPI0B_SS1_B_LSIO_QSPI0B_SS1_B	0x0000004d>;
 	};
 };
	// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
	/*
	* Copyright (c) 2019-2026 TQ-Systems GmbH <linux@ew.tq-group.com>,
	* D-82229 Seefeld, Germany.
	* Author: Alexander Stein
	*/

	#include <dt-bindings/firmware/imx/rsrc.h>
	#include <dt-bindings/gpio/gpio.h>
	#include <dt-bindings/thermal/thermal.h>

	#include "imx8qm.dtsi"

	/ {
	model = "TQ-Systems i.MX8QM TQMa8QM";
	compatible = "tq,imx8qm-tqma8qm", "fsl,imx8qm";

	/* Due to missing workaround for ERR050104 */
	cpus {
	/delete-node/ cpu-map;
	/delete-node/ cpu@100;
	/delete-node/ cpu@101;
	};

	memory@80000000 {
	device_type = "memory";
	/*
	* DRAM base addr, size : 1024 MiB DRAM
	* should be corrected by bootloader
	*/
	reg = <0x00000000 0x80000000 0 0x40000000>;
	};

	reg_tqma8x_v3v3: regulator-tqma8x-v3v3 {
	compatible = "regulator-fixed";
	regulator-name = "V_3V3";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	regulator-always-on;
	};

	/* SW7 controlled by SCU */
	reg_1v8_io1: regulator-v1v8-io1 {
	compatible = "regulator-fixed";
	regulator-name = "V_1V8_IO1";
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	regulator-always-on;
	};

	/* LDO4 controlled by SCU */
	reg_3v3_emmc: regulator-v3v3-emmc {
	compatible = "regulator-fixed";
	regulator-name = "V_3V3_EMMC";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	regulator-always-on;
	};
	};

	&acm {
	status = "okay";
	};

	&adc0 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_adc0>;
	vref-supply = <&reg_vref_v1v8>;
	status = "okay";
	};

	/* TQMa8QM only uses industrial grade, reduce trip points accordingly */
	&cpu_alert0 {
	temperature = <95000>;
	};

	&cpu_crit0 {
	temperature = <100000>;
	};

	&cpu_alert1 {
	temperature = <95000>;
	};

	&cpu_crit1 {
	temperature = <100000>;
	};

	&gpu_alert0 {
	temperature = <95000>;
	};

	&gpu_crit0 {
	temperature = <100000>;
	};

	&gpu_alert1 {
	temperature = <95000>;
	};

	&gpu_crit1 {
	temperature = <100000>;
	};

	&drc_alert0 {
	temperature = <95000>;
	};

	&drc_crit0 {
	temperature = <100000>;
	};
	/* end of temperature grade adjustments */

	&flexspi0 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_flexspi0>;
	status = "okay";

	flash0: flash@0 {
	compatible = "jedec,spi-nor";
	reg = <0>;
	spi-max-frequency = <66000000>;
	spi-tx-bus-width = <4>;
	spi-rx-bus-width = <4>;
	vcc-supply = <&reg_1v8_io1>;

	partitions {
	compatible = "fixed-partitions";
	#address-cells = <1>;
	#size-cells = <1>;
	};
	};
	};

	&i2c1 {
	clock-frequency = <400000>;
	pinctrl-names = "default", "gpio";
	pinctrl-0 = <&pinctrl_lpi2c1>;
	pinctrl-1 = <&pinctrl_lpi2c1gpio>;
	scl-gpios = <&lsio_gpio0 14 (GPIO_ACTIVE_HIGH \| GPIO_OPEN_DRAIN)>;
	sda-gpios = <&lsio_gpio0 15 (GPIO_ACTIVE_HIGH \| GPIO_OPEN_DRAIN)>;
	status = "okay";

	se97: temperature-sensor@1b {
	compatible = "nxp,se97b", "jedec,jc-42.4-temp";
	reg = <0x1b>;
	};

	pcf85063: rtc@51 {
	compatible = "nxp,pcf85063a";
	reg = <0x51>;
	quartz-load-femtofarads = <7000>;
	};

	at24c02: eeprom@53 {
	compatible = "nxp,se97b", "atmel,24c02";
	reg = <0x53>;
	pagesize = <16>;
	read-only;
	vcc-supply = <&reg_tqma8x_v3v3>;
	};

	m24c64: eeprom@57 {
	compatible = "atmel,24c64";
	reg = <0x57>;
	pagesize = <32>;
	vcc-supply = <&reg_tqma8x_v3v3>;
	};
	};

	&mu_m0 {
	status = "okay";
	};

	&mu1_m0 {
	status = "okay";
	};

	&mu2_m0 {
	status = "okay";
	};

	&thermal_zones {
	/delete-node/ cpu1-thermal;

	pmic0-thermal {
	polling-delay-passive = <250>;
	polling-delay = <2000>;
	thermal-sensors = <&tsens IMX_SC_R_PMIC_0>;

	trips {
	pmic_alert0: trip0 {
	temperature = <110000>;
	hysteresis = <2000>;
	type = "passive";
	};
	pmic_crit0: trip1 {
	temperature = <125000>;
	hysteresis = <2000>;
	type = "critical";
	};
	};

	cooling-maps {
	map0 {
	trip = <&pmic_alert0>;
	cooling-device =
	<&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	<&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	<&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	<&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
	};
	};
	};
	};

	&usdhc1 {
	pinctrl-names = "default", "state_100mhz", "state_200mhz";
	pinctrl-0 = <&pinctrl_usdhc1>;
	pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
	pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
	bus-width = <8>;
	vmmc-supply = <&reg_3v3_emmc>;
	vqmmc-supply = <&reg_1v8_io1>;
	no-sd;
	no-sdio;
	non-removable;
	status = "okay";
	};

	&vpu {
	compatible = "nxp,imx8qm-vpu";
	status = "okay";
	};

	&vpu_core0 {
	memory-region = <&decoder_boot>, <&decoder_rpc>;
	status = "okay";
	};

	&vpu_core1 {
	memory-region = <&encoder1_boot>, <&encoder1_rpc>;
	status = "okay";
	};

	&vpu_core2 {
	memory-region = <&encoder2_boot>, <&encoder2_rpc>;
	status = "okay";
	};

	&iomuxc {
	pinctrl_lpi2c1: lpi2c1grp {
	fsl,pins = <IMX8QM_GPT0_CAPTURE_DMA_I2C1_SDA 0x0600004d>,
	<IMX8QM_GPT0_CLK_DMA_I2C1_SCL 0x0600004d>;
	};

	pinctrl_lpi2c1gpio: lpi2c1gpiogrp {
	fsl,pins = <IMX8QM_GPT0_CAPTURE_LSIO_GPIO0_IO15 0x0600004d>,
	<IMX8QM_GPT0_CLK_LSIO_GPIO0_IO14 0x0600004d>;
	};

	pinctrl_usdhc1: usdhc1grp {
	fsl,pins = <IMX8QM_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041>,
	<IMX8QM_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021>,
	<IMX8QM_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021>,
	<IMX8QM_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021>,
	<IMX8QM_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021>,
	<IMX8QM_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021>,
	<IMX8QM_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021>,
	<IMX8QM_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021>,
	<IMX8QM_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021>,
	<IMX8QM_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021>,
	<IMX8QM_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000041>,
	<IMX8QM_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000021>;
	};

	pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
	fsl,pins = <IMX8QM_EMMC0_CLK_CONN_EMMC0_CLK 0x06000040>,
	<IMX8QM_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021>,
	<IMX8QM_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021>,
	<IMX8QM_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021>,
	<IMX8QM_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021>,
	<IMX8QM_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021>,
	<IMX8QM_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021>,
	<IMX8QM_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021>,
	<IMX8QM_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021>,
	<IMX8QM_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021>,
	<IMX8QM_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000041>,
	<IMX8QM_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000021>;
	};

	pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
	fsl,pins = <IMX8QM_EMMC0_CLK_CONN_EMMC0_CLK 0x06000040>,
	<IMX8QM_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021>,
	<IMX8QM_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021>,
	<IMX8QM_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021>,
	<IMX8QM_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021>,
	<IMX8QM_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021>,
	<IMX8QM_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021>,
	<IMX8QM_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021>,
	<IMX8QM_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021>,
	<IMX8QM_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021>,
	<IMX8QM_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000041>,
	<IMX8QM_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000021>;
	};

	pinctrl_flexspi0: flexspi0grp {
	fsl,pins = <IMX8QM_QSPI0A_DATA0_LSIO_QSPI0A_DATA0 0x0000004d>,
	<IMX8QM_QSPI0A_DATA1_LSIO_QSPI0A_DATA1 0x0000004d>,
	<IMX8QM_QSPI0A_DATA2_LSIO_QSPI0A_DATA2 0x0000004d>,
	<IMX8QM_QSPI0A_DATA3_LSIO_QSPI0A_DATA3 0x0000004d>,
	<IMX8QM_QSPI0A_DQS_LSIO_QSPI0A_DQS 0x0000004d>,
	<IMX8QM_QSPI0A_SS0_B_LSIO_QSPI0A_SS0_B 0x0000004d>,
	<IMX8QM_QSPI0A_SS1_B_LSIO_QSPI0A_SS1_B 0x0000004d>,
	<IMX8QM_QSPI0A_SCLK_LSIO_QSPI0A_SCLK 0x0000004d>,
	<IMX8QM_QSPI0B_SCLK_LSIO_QSPI0B_SCLK 0x0000004d>,
	<IMX8QM_QSPI0B_DATA0_LSIO_QSPI0B_DATA0 0x0000004d>,
	<IMX8QM_QSPI0B_DATA1_LSIO_QSPI0B_DATA1 0x0000004d>,
	<IMX8QM_QSPI0B_DATA2_LSIO_QSPI0B_DATA2 0x0000004d>,
	<IMX8QM_QSPI0B_DATA3_LSIO_QSPI0B_DATA3 0x0000004d>,
	<IMX8QM_QSPI0B_DQS_LSIO_QSPI0B_DQS 0x0000004d>,
	<IMX8QM_QSPI0B_SS0_B_LSIO_QSPI0B_SS0_B 0x0000004d>,
	<IMX8QM_QSPI0B_SS1_B_LSIO_QSPI0B_SS1_B 0x0000004d>;
	};
	};