| // SPDX-License-Identifier: (GPL-2.0+ OR MIT) |
| /* |
| * Copyright 2024 NXP |
| */ |
| |
| /dts-v1/; |
| |
| #include <dt-bindings/usb/pd.h> |
| #include "imx95.dtsi" |
| |
| #define BRD_SM_CTRL_SD3_WAKE 0x8000 |
| #define BRD_SM_CTRL_PCIE1_WAKE 0x8001 |
| #define BRD_SM_CTRL_BT_WAKE 0x8002 |
| #define BRD_SM_CTRL_PCIE2_WAKE 0x8003 |
| #define BRD_SM_CTRL_BUTTON 0x8004 |
| |
| / { |
| compatible = "fsl,imx95-15x15-ab2", "fsl,imx95"; |
| model = "NXP i.MX95 CPU on AB2"; |
| |
| aliases { |
| ethernet0 = &enetc_port0; |
| gpio0 = &gpio1; |
| gpio1 = &gpio2; |
| gpio2 = &gpio3; |
| gpio3 = &gpio4; |
| gpio4 = &gpio5; |
| i2c0 = &lpi2c1; |
| i2c1 = &lpi2c2; |
| i2c2 = &lpi2c3; |
| i2c3 = &lpi2c4; |
| mmc0 = &usdhc1; |
| mmc1 = &usdhc2; |
| serial0 = &lpuart1; |
| }; |
| |
| chosen { |
| #address-cells = <2>; |
| #size-cells = <2>; |
| stdout-path = &lpuart1; |
| }; |
| |
| reg_ab2_ana_pwr: regulator-ab2-ana-pwr { |
| compatible = "regulator-fixed"; |
| regulator-name = "ab2_ana_pwr"; |
| regulator-always-on; |
| regulator-max-microvolt = <3300000>; |
| regulator-min-microvolt = <3300000>; |
| gpio = <&pcal6524 1 GPIO_ACTIVE_HIGH>; |
| enable-active-high; |
| }; |
| |
| reg_ab2_vdd_pwr_5v0: regulator-ab2-vdd-pwr-5v0 { |
| compatible = "regulator-fixed"; |
| regulator-name = "ab2_vdd_pwr_5v0"; |
| regulator-always-on; |
| regulator-max-microvolt = <3300000>; |
| regulator-min-microvolt = <3300000>; |
| gpio = <&pcal6524 2 GPIO_ACTIVE_HIGH>; |
| enable-active-high; |
| }; |
| |
| reg_usdhc2_vmmc: regulator-usdhc2 { |
| compatible = "regulator-fixed"; |
| regulator-name = "VDD_SD2_3V3"; |
| off-on-delay-us = <12000>; |
| pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; |
| pinctrl-names = "default"; |
| regulator-max-microvolt = <3300000>; |
| regulator-min-microvolt = <3300000>; |
| gpio = <&gpio3 7 GPIO_ACTIVE_HIGH>; |
| enable-active-high; |
| }; |
| |
| reserved-memory { |
| ranges; |
| #address-cells = <2>; |
| #size-cells = <2>; |
| |
| linux_cma: linux,cma { |
| compatible = "shared-dma-pool"; |
| alloc-ranges = <0 0x80000000 0 0x7f000000>; |
| reusable; |
| size = <0 0x3c000000>; |
| linux,cma-default; |
| }; |
| |
| vpu_boot: vpu-boot@a0000000 { |
| reg = <0 0xa0000000 0 0x100000>; |
| no-map; |
| }; |
| }; |
| |
| sound-ak4458 { |
| compatible = "fsl,imx-audio-card"; |
| model = "ak4458-audio"; |
| |
| pri-dai-link { |
| format = "i2s"; |
| link-name = "akcodec"; |
| fsl,mclk-equal-bclk; |
| |
| codec { |
| sound-dai = <&ak4458_1>, <&ak4458_2>; |
| }; |
| |
| cpu { |
| sound-dai = <&sai2>; |
| }; |
| }; |
| }; |
| |
| sound-ak5552 { |
| compatible = "fsl,imx-audio-card"; |
| model = "ak5552-audio"; |
| |
| pri-dai-link { |
| format = "i2s"; |
| link-name = "akcodec"; |
| fsl,mclk-equal-bclk; |
| |
| codec { |
| sound-dai = <&ak5552>; |
| }; |
| |
| cpu { |
| sound-dai = <&sai3>; |
| }; |
| }; |
| }; |
| |
| sound-micfil { |
| compatible = "fsl,imx-audio-card"; |
| model = "micfil-audio"; |
| |
| pri-dai-link { |
| format = "i2s"; |
| link-name = "micfil hifi"; |
| |
| cpu { |
| sound-dai = <&micfil>; |
| }; |
| }; |
| }; |
| |
| sound-xcvr { |
| compatible = "fsl,imx-audio-card"; |
| model = "imx-audio-xcvr"; |
| |
| pri-dai-link { |
| link-name = "XCVR PCM"; |
| |
| cpu { |
| sound-dai = <&xcvr>; |
| }; |
| }; |
| }; |
| |
| memory@80000000 { |
| reg = <0x0 0x80000000 0 0x80000000>; |
| device_type = "memory"; |
| }; |
| }; |
| |
| &enetc_port0 { |
| phy-handle = <ðphy0>; |
| phy-mode = "rgmii-id"; |
| pinctrl-0 = <&pinctrl_enetc0>; |
| pinctrl-names = "default"; |
| status = "okay"; |
| }; |
| |
| &lpi2c1 { |
| clock-frequency = <400000>; |
| pinctrl-0 = <&pinctrl_lpi2c1>; |
| pinctrl-names = "default"; |
| status = "disabled"; |
| }; |
| |
| &lpi2c2 { |
| clock-frequency = <400000>; |
| pinctrl-0 = <&pinctrl_lpi2c2>; |
| pinctrl-names = "default"; |
| status = "okay"; |
| |
| pcal6524: gpio@22 { |
| compatible = "nxp,pcal6524"; |
| reg = <0x22>; |
| #interrupt-cells = <2>; |
| interrupt-controller; |
| interrupt-parent = <&gpio5>; |
| interrupts = <14 IRQ_TYPE_LEVEL_LOW>; |
| #gpio-cells = <2>; |
| gpio-controller; |
| pinctrl-0 = <&pinctrl_pcal6524>; |
| pinctrl-names = "default"; |
| }; |
| }; |
| |
| &lpi2c3 { |
| clock-frequency = <400000>; |
| pinctrl-0 = <&pinctrl_lpi2c3>; |
| pinctrl-names = "default"; |
| status = "okay"; |
| |
| ak4458_1: audio-codec@10 { |
| compatible = "asahi-kasei,ak4458"; |
| reg = <0x10>; |
| #sound-dai-cells = <0>; |
| AVDD-supply = <®_ab2_ana_pwr>; |
| DVDD-supply = <®_ab2_ana_pwr>; |
| reset-gpios = <&pca6416 4 GPIO_ACTIVE_LOW>; |
| sound-name-prefix = "0"; |
| }; |
| |
| ak4458_3: audio-codec@11 { |
| compatible = "asahi-kasei,ak4458"; |
| reg = <0x11>; |
| #sound-dai-cells = <0>; |
| AVDD-supply = <®_ab2_ana_pwr>; |
| DVDD-supply = <®_ab2_ana_pwr>; |
| reset-gpios = <&pca6416 4 GPIO_ACTIVE_LOW>; |
| status = "disabled"; |
| }; |
| |
| ak4458_2: audio-codec@12 { |
| compatible = "asahi-kasei,ak4458"; |
| reg = <0x12>; |
| #sound-dai-cells = <0>; |
| AVDD-supply = <®_ab2_ana_pwr>; |
| DVDD-supply = <®_ab2_ana_pwr>; |
| reset-gpios = <&pca6416 4 GPIO_ACTIVE_LOW>; |
| sound-name-prefix = "1"; |
| }; |
| |
| ak5552: audio-codec@13 { |
| compatible = "asahi-kasei,ak5552"; |
| reg = <0x13>; |
| #sound-dai-cells = <0>; |
| AVDD-supply = <®_ab2_ana_pwr>; |
| DVDD-supply = <®_ab2_ana_pwr>; |
| reset-gpios = <&pca6416 3 GPIO_ACTIVE_LOW>; |
| }; |
| |
| pca6416: gpio@20 { |
| compatible = "ti,tca6416"; |
| reg = <0x20>; |
| #gpio-cells = <2>; |
| gpio-controller; |
| }; |
| }; |
| |
| &lpi2c4 { |
| clock-frequency = <400000>; |
| pinctrl-0 = <&pinctrl_lpi2c4>; |
| pinctrl-names = "default"; |
| status = "okay"; |
| }; |
| |
| &lpuart1 { |
| /* console */ |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_uart1>; |
| status = "okay"; |
| }; |
| |
| &micfil { |
| assigned-clocks = <&scmi_clk IMX95_CLK_AUDIOPLL1_VCO>, |
| <&scmi_clk IMX95_CLK_AUDIOPLL2_VCO>, |
| <&scmi_clk IMX95_CLK_AUDIOPLL1>, |
| <&scmi_clk IMX95_CLK_AUDIOPLL2>, |
| <&scmi_clk IMX95_CLK_PDM>; |
| assigned-clock-parents = <0>, <0>, <0>, <0>, |
| <&scmi_clk IMX95_CLK_AUDIOPLL1>; |
| assigned-clock-rates = <3932160000>, |
| <3612672000>, <393216000>, |
| <361267200>, <49152000>; |
| #sound-dai-cells = <0>; |
| pinctrl-0 = <&pinctrl_pdm>; |
| pinctrl-names = "default"; |
| status = "okay"; |
| }; |
| |
| &netc_blk_ctrl { |
| status = "okay"; |
| }; |
| |
| &netc_emdio { |
| pinctrl-0 = <&pinctrl_emdio>; |
| pinctrl-names = "default"; |
| status = "okay"; |
| |
| ethphy0: ethernet-phy@1 { |
| reg = <1>; |
| reset-assert-us = <10000>; |
| reset-deassert-us = <80000>; |
| reset-gpios = <&pcal6524 4 GPIO_ACTIVE_LOW>; |
| realtek,clkout-disable; |
| }; |
| }; |
| |
| &netcmix_blk_ctrl { |
| status = "okay"; |
| }; |
| |
| &sai2 { |
| clocks = <&scmi_clk IMX95_CLK_BUSNETCMIX>, <&dummy>, |
| <&scmi_clk IMX95_CLK_SAI2>, <&dummy>, |
| <&dummy>, <&scmi_clk IMX95_CLK_AUDIOPLL1>, |
| <&scmi_clk IMX95_CLK_AUDIOPLL2>; |
| clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3", "pll8k", "pll11k"; |
| assigned-clocks = <&scmi_clk IMX95_CLK_AUDIOPLL1_VCO>, |
| <&scmi_clk IMX95_CLK_AUDIOPLL2_VCO>, |
| <&scmi_clk IMX95_CLK_AUDIOPLL1>, |
| <&scmi_clk IMX95_CLK_AUDIOPLL2>, |
| <&scmi_clk IMX95_CLK_SAI2>; |
| assigned-clock-parents = <0>, <0>, <0>, <0>, |
| <&scmi_clk IMX95_CLK_AUDIOPLL1>; |
| assigned-clock-rates = <3932160000>, |
| <3612672000>, <393216000>, |
| <361267200>, <12288000>; |
| #sound-dai-cells = <0>; |
| pinctrl-0 = <&pinctrl_sai2>; |
| pinctrl-names = "default"; |
| fsl,sai-asynchronous; |
| fsl,sai-mclk-direction-output; |
| status = "okay"; |
| }; |
| |
| &sai3 { |
| clocks = <&scmi_clk IMX95_CLK_BUSNETCMIX>, <&dummy>, |
| <&scmi_clk IMX95_CLK_SAI3>, <&dummy>, |
| <&dummy>, <&scmi_clk IMX95_CLK_AUDIOPLL1>, |
| <&scmi_clk IMX95_CLK_AUDIOPLL2>; |
| clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3", "pll8k", "pll11k"; |
| assigned-clocks = <&scmi_clk IMX95_CLK_AUDIOPLL1_VCO>, |
| <&scmi_clk IMX95_CLK_AUDIOPLL2_VCO>, |
| <&scmi_clk IMX95_CLK_AUDIOPLL1>, |
| <&scmi_clk IMX95_CLK_AUDIOPLL2>, |
| <&scmi_clk IMX95_CLK_SAI3>; |
| assigned-clock-parents = <0>, <0>, <0>, <0>, |
| <&scmi_clk IMX95_CLK_AUDIOPLL1>; |
| assigned-clock-rates = <3932160000>, |
| <3612672000>, <393216000>, |
| <361267200>, <12288000>; |
| #sound-dai-cells = <0>; |
| pinctrl-0 = <&pinctrl_sai3>; |
| pinctrl-names = "default"; |
| fsl,sai-asynchronous; |
| fsl,sai-mclk-direction-output; |
| status = "okay"; |
| }; |
| |
| &sai5 { |
| assigned-clocks = <&scmi_clk IMX95_CLK_AUDIOPLL1_VCO>, |
| <&scmi_clk IMX95_CLK_AUDIOPLL2_VCO>, |
| <&scmi_clk IMX95_CLK_AUDIOPLL1>, |
| <&scmi_clk IMX95_CLK_AUDIOPLL2>, |
| <&scmi_clk IMX95_CLK_SAI5>; |
| assigned-clock-parents = <0>, <0>, <0>, <0>, |
| <&scmi_clk IMX95_CLK_AUDIOPLL1>; |
| assigned-clock-rates = <3932160000>, |
| <3612672000>, <393216000>, |
| <361267200>, <12288000>; |
| #sound-dai-cells = <0>; |
| pinctrl-0 = <&pinctrl_sai5>; |
| pinctrl-names = "default"; |
| fsl,sai-mclk-direction-output; |
| status = "okay"; |
| }; |
| |
| &scmi_iomuxc { |
| pinctrl_emdio: emdiogrp { |
| fsl,pins = < |
| IMX95_PAD_ENET1_MDC__NETCMIX_TOP_NETC_MDC 0x50e |
| IMX95_PAD_ENET1_MDIO__NETCMIX_TOP_NETC_MDIO 0x90e |
| >; |
| }; |
| |
| pinctrl_enetc0: enetc0grp { |
| fsl,pins = < |
| IMX95_PAD_ENET1_TD3__NETCMIX_TOP_ETH0_RGMII_TD3 0x50e |
| IMX95_PAD_ENET1_TD2__NETCMIX_TOP_ETH0_RGMII_TD2 0x50e |
| IMX95_PAD_ENET1_TD1__NETCMIX_TOP_ETH0_RGMII_TD1 0x50e |
| IMX95_PAD_ENET1_TD0__NETCMIX_TOP_ETH0_RGMII_TD0 0x50e |
| IMX95_PAD_ENET1_TX_CTL__NETCMIX_TOP_ETH0_RGMII_TX_CTL 0x57e |
| IMX95_PAD_ENET1_TXC__NETCMIX_TOP_ETH0_RGMII_TX_CLK 0x58e |
| IMX95_PAD_ENET1_RX_CTL__NETCMIX_TOP_ETH0_RGMII_RX_CTL 0x57e |
| IMX95_PAD_ENET1_RXC__NETCMIX_TOP_ETH0_RGMII_RX_CLK 0x58e |
| IMX95_PAD_ENET1_RD0__NETCMIX_TOP_ETH0_RGMII_RD0 0x57e |
| IMX95_PAD_ENET1_RD1__NETCMIX_TOP_ETH0_RGMII_RD1 0x57e |
| IMX95_PAD_ENET1_RD2__NETCMIX_TOP_ETH0_RGMII_RD2 0x57e |
| IMX95_PAD_ENET1_RD3__NETCMIX_TOP_ETH0_RGMII_RD3 0x57e |
| >; |
| }; |
| |
| pinctrl_lpi2c1: lpi2c1grp { |
| fsl,pins = < |
| IMX95_PAD_I2C1_SCL__AONMIX_TOP_LPI2C1_SCL 0x40000b9e |
| IMX95_PAD_I2C1_SDA__AONMIX_TOP_LPI2C1_SDA 0x40000b9e |
| >; |
| }; |
| |
| pinctrl_lpi2c2: lpi2c2grp { |
| fsl,pins = < |
| IMX95_PAD_I2C2_SCL__AONMIX_TOP_LPI2C2_SCL 0x40000b9e |
| IMX95_PAD_I2C2_SDA__AONMIX_TOP_LPI2C2_SDA 0x40000b9e |
| >; |
| }; |
| |
| pinctrl_lpi2c3: lpi2c3grp { |
| fsl,pins = < |
| IMX95_PAD_GPIO_IO28__LPI2C3_SDA 0x40000b9e |
| IMX95_PAD_GPIO_IO29__LPI2C3_SCL 0x40000b9e |
| >; |
| }; |
| |
| pinctrl_lpi2c4: lpi2c4grp { |
| fsl,pins = < |
| IMX95_PAD_GPIO_IO30__LPI2C4_SDA 0x40000b9e |
| IMX95_PAD_GPIO_IO31__LPI2C4_SCL 0x40000b9e |
| >; |
| }; |
| |
| pinctrl_pcal6524: pcal6524grp { |
| fsl,pins = < |
| IMX95_PAD_GPIO_IO34__GPIO5_IO_BIT14 0x31e |
| >; |
| }; |
| |
| pinctrl_pdm: pdmgrp { |
| fsl,pins = < |
| IMX95_PAD_PDM_CLK__AONMIX_TOP_PDM_CLK 0x31e |
| IMX95_PAD_PDM_BIT_STREAM0__AONMIX_TOP_PDM_BIT_STREAM_BIT0 0x31e |
| IMX95_PAD_GPIO_IO06__AONMIX_TOP_PDM_BIT_STREAM_BIT1 0x31e |
| IMX95_PAD_GPIO_IO12__AONMIX_TOP_PDM_BIT_STREAM_BIT2 0x31e |
| IMX95_PAD_GPIO_IO13__AONMIX_TOP_PDM_BIT_STREAM_BIT3 0x31e |
| >; |
| }; |
| |
| pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { |
| fsl,pins = < |
| IMX95_PAD_SD2_RESET_B__GPIO3_IO_BIT7 0x31e |
| >; |
| }; |
| |
| pinctrl_sai2: sai2grp { |
| fsl,pins = < |
| IMX95_PAD_ENET2_RD2__NETCMIX_TOP_SAI2_MCLK 0x31e |
| IMX95_PAD_ENET2_MDIO__NETCMIX_TOP_SAI2_RX_BCLK 0x31e |
| IMX95_PAD_ENET2_MDC__NETCMIX_TOP_SAI2_RX_SYNC 0x31e |
| IMX95_PAD_ENET2_TD3__NETCMIX_TOP_SAI2_RX_DATA_BIT0 0x31e |
| IMX95_PAD_ENET2_TD2__NETCMIX_TOP_SAI2_RX_DATA_BIT1 0x31e |
| IMX95_PAD_ENET2_TD1__NETCMIX_TOP_SAI2_RX_DATA_BIT2 0x31e |
| IMX95_PAD_ENET2_TD0__NETCMIX_TOP_SAI2_RX_DATA_BIT3 0x31e |
| IMX95_PAD_ENET2_TXC__NETCMIX_TOP_SAI2_TX_BCLK 0x31e |
| IMX95_PAD_ENET2_TX_CTL__NETCMIX_TOP_SAI2_TX_SYNC 0x31e |
| IMX95_PAD_ENET2_RX_CTL__NETCMIX_TOP_SAI2_TX_DATA_BIT0 0x31e |
| IMX95_PAD_ENET2_RXC__NETCMIX_TOP_SAI2_TX_DATA_BIT1 0x31e |
| IMX95_PAD_ENET2_RD0__NETCMIX_TOP_SAI2_TX_DATA_BIT2 0x31e |
| IMX95_PAD_ENET2_RD1__NETCMIX_TOP_SAI2_TX_DATA_BIT3 0x31e |
| IMX95_PAD_XSPI1_DATA0__NETCMIX_TOP_SAI2_TX_DATA_BIT4 0x31e |
| IMX95_PAD_XSPI1_DATA1__NETCMIX_TOP_SAI2_TX_DATA_BIT5 0x31e |
| IMX95_PAD_XSPI1_DATA2__NETCMIX_TOP_SAI2_TX_DATA_BIT6 0x31e |
| IMX95_PAD_XSPI1_DATA3__NETCMIX_TOP_SAI2_TX_DATA_BIT7 0x31e |
| >; |
| }; |
| |
| pinctrl_sai3: sai3grp { |
| fsl,pins = < |
| IMX95_PAD_GPIO_IO17__SAI3_MCLK 0x31e |
| IMX95_PAD_GPIO_IO18__SAI3_RX_BCLK 0x31e |
| IMX95_PAD_GPIO_IO19__SAI3_RX_SYNC 0x31e |
| IMX95_PAD_GPIO_IO20__SAI3_RX_DATA_BIT0 0x31e |
| >; |
| }; |
| |
| pinctrl_sai5: sai5grp { |
| fsl,pins = < |
| IMX95_PAD_XSPI1_DATA4__SAI5_TX_DATA_BIT0 0x31e |
| IMX95_PAD_XSPI1_DATA7__SAI5_RX_DATA_BIT0 0x31e |
| IMX95_PAD_XSPI1_SS1_B__SAI5_RX_BCLK 0x31e |
| IMX95_PAD_XSPI1_DQS__SAI5_RX_SYNC 0x31e |
| |
| >; |
| }; |
| |
| pinctrl_spdif: spdifgrp { |
| fsl,pins = < |
| IMX95_PAD_GPIO_IO22__SPDIF_IN 0x31e |
| IMX95_PAD_GPIO_IO23__SPDIF_OUT 0x31e |
| >; |
| }; |
| |
| pinctrl_uart1: uart1grp { |
| fsl,pins = < |
| IMX95_PAD_UART1_RXD__AONMIX_TOP_LPUART1_RX 0x31e |
| IMX95_PAD_UART1_TXD__AONMIX_TOP_LPUART1_TX 0x31e |
| >; |
| }; |
| |
| pinctrl_usdhc1: usdhc1grp { |
| fsl,pins = < |
| IMX95_PAD_SD1_CLK__USDHC1_CLK 0x158e |
| IMX95_PAD_SD1_CMD__USDHC1_CMD 0x138e |
| IMX95_PAD_SD1_DATA0__USDHC1_DATA0 0x138e |
| IMX95_PAD_SD1_DATA1__USDHC1_DATA1 0x138e |
| IMX95_PAD_SD1_DATA2__USDHC1_DATA2 0x138e |
| IMX95_PAD_SD1_DATA3__USDHC1_DATA3 0x138e |
| IMX95_PAD_SD1_DATA4__USDHC1_DATA4 0x138e |
| IMX95_PAD_SD1_DATA5__USDHC1_DATA5 0x138e |
| IMX95_PAD_SD1_DATA6__USDHC1_DATA6 0x138e |
| IMX95_PAD_SD1_DATA7__USDHC1_DATA7 0x138e |
| IMX95_PAD_SD1_STROBE__USDHC1_STROBE 0x158e |
| >; |
| }; |
| |
| pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { |
| fsl,pins = < |
| IMX95_PAD_SD1_CLK__USDHC1_CLK 0x158e |
| IMX95_PAD_SD1_CMD__USDHC1_CMD 0x138e |
| IMX95_PAD_SD1_DATA0__USDHC1_DATA0 0x138e |
| IMX95_PAD_SD1_DATA1__USDHC1_DATA1 0x138e |
| IMX95_PAD_SD1_DATA2__USDHC1_DATA2 0x138e |
| IMX95_PAD_SD1_DATA3__USDHC1_DATA3 0x138e |
| IMX95_PAD_SD1_DATA4__USDHC1_DATA4 0x138e |
| IMX95_PAD_SD1_DATA5__USDHC1_DATA5 0x138e |
| IMX95_PAD_SD1_DATA6__USDHC1_DATA6 0x138e |
| IMX95_PAD_SD1_DATA7__USDHC1_DATA7 0x138e |
| IMX95_PAD_SD1_STROBE__USDHC1_STROBE 0x158e |
| >; |
| }; |
| |
| pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { |
| fsl,pins = < |
| IMX95_PAD_SD1_CLK__USDHC1_CLK 0x15fe |
| IMX95_PAD_SD1_CMD__USDHC1_CMD 0x13fe |
| IMX95_PAD_SD1_DATA0__USDHC1_DATA0 0x13fe |
| IMX95_PAD_SD1_DATA1__USDHC1_DATA1 0x13fe |
| IMX95_PAD_SD1_DATA2__USDHC1_DATA2 0x13fe |
| IMX95_PAD_SD1_DATA3__USDHC1_DATA3 0x13fe |
| IMX95_PAD_SD1_DATA4__USDHC1_DATA4 0x13fe |
| IMX95_PAD_SD1_DATA5__USDHC1_DATA5 0x13fe |
| IMX95_PAD_SD1_DATA6__USDHC1_DATA6 0x13fe |
| IMX95_PAD_SD1_DATA7__USDHC1_DATA7 0x13fe |
| IMX95_PAD_SD1_STROBE__USDHC1_STROBE 0x15fe |
| >; |
| }; |
| |
| pinctrl_usdhc2_gpio: usdhc2gpiogrp { |
| fsl,pins = < |
| IMX95_PAD_SD2_CD_B__GPIO3_IO_BIT0 0x31e |
| >; |
| }; |
| |
| pinctrl_usdhc2: usdhc2grp { |
| fsl,pins = < |
| IMX95_PAD_SD2_CLK__USDHC2_CLK 0x158e |
| IMX95_PAD_SD2_CMD__USDHC2_CMD 0x138e |
| IMX95_PAD_SD2_DATA0__USDHC2_DATA0 0x138e |
| IMX95_PAD_SD2_DATA1__USDHC2_DATA1 0x138e |
| IMX95_PAD_SD2_DATA2__USDHC2_DATA2 0x138e |
| IMX95_PAD_SD2_DATA3__USDHC2_DATA3 0x138e |
| IMX95_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e |
| >; |
| }; |
| |
| pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { |
| fsl,pins = < |
| IMX95_PAD_SD2_CLK__USDHC2_CLK 0x158e |
| IMX95_PAD_SD2_CMD__USDHC2_CMD 0x138e |
| IMX95_PAD_SD2_DATA0__USDHC2_DATA0 0x138e |
| IMX95_PAD_SD2_DATA1__USDHC2_DATA1 0x138e |
| IMX95_PAD_SD2_DATA2__USDHC2_DATA2 0x138e |
| IMX95_PAD_SD2_DATA3__USDHC2_DATA3 0x138e |
| IMX95_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e |
| >; |
| }; |
| |
| pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { |
| fsl,pins = < |
| IMX95_PAD_SD2_CLK__USDHC2_CLK 0x15fe |
| IMX95_PAD_SD2_CMD__USDHC2_CMD 0x13fe |
| IMX95_PAD_SD2_DATA0__USDHC2_DATA0 0x13fe |
| IMX95_PAD_SD2_DATA1__USDHC2_DATA1 0x13fe |
| IMX95_PAD_SD2_DATA2__USDHC2_DATA2 0x13fe |
| IMX95_PAD_SD2_DATA3__USDHC2_DATA3 0x13fe |
| IMX95_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e |
| >; |
| }; |
| }; |
| |
| &scmi_misc { |
| nxp,ctrl-ids = <BRD_SM_CTRL_SD3_WAKE 1>, |
| <BRD_SM_CTRL_PCIE1_WAKE 1>, |
| <BRD_SM_CTRL_BT_WAKE 1>, |
| <BRD_SM_CTRL_PCIE2_WAKE 1>, |
| <BRD_SM_CTRL_BUTTON 1>; |
| }; |
| |
| &usb3 { |
| status = "okay"; |
| }; |
| |
| &usb3_dwc3 { |
| adp-disable; |
| dr_mode = "host"; |
| hnp-disable; |
| srp-disable; |
| snps,dis-u1-entry-quirk; |
| snps,dis-u2-entry-quirk; |
| status = "okay"; |
| }; |
| |
| &usb3_phy { |
| status = "okay"; |
| }; |
| |
| &usdhc1 { |
| bus-width = <8>; |
| non-removable; |
| no-sd; |
| no-sdio; |
| pinctrl-0 = <&pinctrl_usdhc1>; |
| pinctrl-1 = <&pinctrl_usdhc1_100mhz>; |
| pinctrl-2 = <&pinctrl_usdhc1_200mhz>; |
| pinctrl-3 = <&pinctrl_usdhc1>; |
| pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; |
| fsl,tuning-step = <1>; |
| status = "okay"; |
| }; |
| |
| &usdhc2 { |
| bus-width = <4>; |
| cd-gpios = <&gpio3 00 GPIO_ACTIVE_LOW>; |
| pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; |
| pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; |
| pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; |
| pinctrl-3 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; |
| pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; |
| vmmc-supply = <®_usdhc2_vmmc>; |
| status = "okay"; |
| }; |
| |
| &xcvr { |
| clocks = <&scmi_clk IMX95_CLK_BUSWAKEUP>, |
| <&scmi_clk IMX95_CLK_SPDIF>, |
| <&dummy>, |
| <&scmi_clk IMX95_CLK_AUDIOXCVR>, |
| <&scmi_clk IMX95_CLK_AUDIOPLL1>, |
| <&scmi_clk IMX95_CLK_AUDIOPLL2>; |
| clock-names = "ipg", "phy", "spba", "pll_ipg", "pll8k", "pll11k"; |
| assigned-clocks = <&scmi_clk IMX95_CLK_AUDIOPLL1_VCO>, |
| <&scmi_clk IMX95_CLK_AUDIOPLL2_VCO>, |
| <&scmi_clk IMX95_CLK_AUDIOPLL1>, |
| <&scmi_clk IMX95_CLK_AUDIOPLL2>, |
| <&scmi_clk IMX95_CLK_SPDIF>, |
| <&scmi_clk IMX95_CLK_AUDIOXCVR>; |
| assigned-clock-parents = <0>, <0>, <0>, <0>, |
| <&scmi_clk IMX95_CLK_AUDIOPLL1>, |
| <&scmi_clk IMX95_CLK_SYSPLL1_PFD1_DIV2>; |
| assigned-clock-rates = <3932160000>, <3612672000>, |
| <393216000>, <361267200>, |
| <12288000>, <0>; |
| #sound-dai-cells = <0>; |
| pinctrl-0 = <&pinctrl_spdif>; |
| pinctrl-names = "default"; |
| status = "okay"; |
| }; |
