| // SPDX-License-Identifier: (GPL-2.0-only OR MIT) |
| /* |
| * Copyright 2025-2026 NXP |
| */ |
| |
| #include <dt-bindings/dma/fsl-edma.h> |
| #include <dt-bindings/gpio/gpio.h> |
| #include <dt-bindings/interrupt-controller/arm-gic.h> |
| |
| #include "imx952-clock.h" |
| #include "imx952-pinfunc.h" |
| #include "imx952-power.h" |
| |
| / { |
| interrupt-parent = <&gic>; |
| #address-cells = <2>; |
| #size-cells = <2>; |
| |
| clk_ext1: clock-ext1 { |
| compatible = "fixed-clock"; |
| #clock-cells = <0>; |
| clock-frequency = <133000000>; |
| clock-output-names = "clk_ext1"; |
| }; |
| |
| clk_dummy: clock-dummy { |
| compatible = "fixed-clock"; |
| #clock-cells = <0>; |
| clock-frequency = <0>; |
| clock-output-names = "dummy"; |
| }; |
| |
| clk_ldb_pll_pixel: clock-ldb-pll-div7 { |
| compatible = "fixed-factor-clock"; |
| clocks = <&scmi_clk IMX952_CLK_LDBPLL>; |
| #clock-cells = <0>; |
| clock-div = <7>; |
| clock-mult = <1>; |
| clock-output-names = "ldb_pll_div7"; |
| }; |
| |
| clk_osc_24m: clock-osc-24m { |
| compatible = "fixed-clock"; |
| #clock-cells = <0>; |
| clock-frequency = <24000000>; |
| clock-output-names = "osc_24m"; |
| }; |
| |
| cpus { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| idle-states { |
| entry-method = "psci"; |
| |
| cpu_pd_wait: cpu-pd-wait { |
| compatible = "arm,idle-state"; |
| arm,psci-suspend-param = <0x0010033>; |
| local-timer-stop; |
| entry-latency-us = <1000>; |
| exit-latency-us = <700>; |
| min-residency-us = <2700>; |
| wakeup-latency-us = <1500>; |
| }; |
| }; |
| |
| A55_0: cpu@0 { |
| device_type = "cpu"; |
| compatible = "arm,cortex-a55"; |
| reg = <0x0>; |
| enable-method = "psci"; |
| #cooling-cells = <2>; |
| cpu-idle-states = <&cpu_pd_wait>; |
| power-domains = <&scmi_perf IMX952_PERF_A55>; |
| power-domain-names = "perf"; |
| i-cache-size = <32768>; |
| i-cache-line-size = <64>; |
| i-cache-sets = <128>; |
| d-cache-size = <32768>; |
| d-cache-line-size = <64>; |
| d-cache-sets = <128>; |
| next-level-cache = <&l2_cache_l0>; |
| }; |
| |
| A55_1: cpu@100 { |
| device_type = "cpu"; |
| compatible = "arm,cortex-a55"; |
| reg = <0x100>; |
| enable-method = "psci"; |
| #cooling-cells = <2>; |
| cpu-idle-states = <&cpu_pd_wait>; |
| power-domains = <&scmi_perf IMX952_PERF_A55>; |
| power-domain-names = "perf"; |
| i-cache-size = <32768>; |
| i-cache-line-size = <64>; |
| i-cache-sets = <128>; |
| d-cache-size = <32768>; |
| d-cache-line-size = <64>; |
| d-cache-sets = <128>; |
| next-level-cache = <&l2_cache_l1>; |
| }; |
| |
| A55_2: cpu@200 { |
| device_type = "cpu"; |
| compatible = "arm,cortex-a55"; |
| reg = <0x200>; |
| enable-method = "psci"; |
| #cooling-cells = <2>; |
| cpu-idle-states = <&cpu_pd_wait>; |
| power-domains = <&scmi_perf IMX952_PERF_A55>; |
| power-domain-names = "perf"; |
| i-cache-size = <32768>; |
| i-cache-line-size = <64>; |
| i-cache-sets = <128>; |
| d-cache-size = <32768>; |
| d-cache-line-size = <64>; |
| d-cache-sets = <128>; |
| next-level-cache = <&l2_cache_l2>; |
| }; |
| |
| A55_3: cpu@300 { |
| device_type = "cpu"; |
| compatible = "arm,cortex-a55"; |
| reg = <0x300>; |
| enable-method = "psci"; |
| #cooling-cells = <2>; |
| cpu-idle-states = <&cpu_pd_wait>; |
| power-domains = <&scmi_perf IMX952_PERF_A55>; |
| power-domain-names = "perf"; |
| i-cache-size = <32768>; |
| i-cache-line-size = <64>; |
| i-cache-sets = <128>; |
| d-cache-size = <32768>; |
| d-cache-line-size = <64>; |
| d-cache-sets = <128>; |
| next-level-cache = <&l2_cache_l3>; |
| }; |
| |
| l2_cache_l0: l2-cache-l0 { |
| compatible = "cache"; |
| cache-size = <65536>; |
| cache-line-size = <64>; |
| cache-sets = <256>; |
| cache-level = <2>; |
| cache-unified; |
| next-level-cache = <&l3_cache>; |
| }; |
| |
| l2_cache_l1: l2-cache-l1 { |
| compatible = "cache"; |
| cache-size = <65536>; |
| cache-line-size = <64>; |
| cache-sets = <256>; |
| cache-level = <2>; |
| cache-unified; |
| next-level-cache = <&l3_cache>; |
| }; |
| |
| l2_cache_l2: l2-cache-l2 { |
| compatible = "cache"; |
| cache-size = <65536>; |
| cache-line-size = <64>; |
| cache-sets = <256>; |
| cache-level = <2>; |
| cache-unified; |
| next-level-cache = <&l3_cache>; |
| }; |
| |
| l2_cache_l3: l2-cache-l3 { |
| compatible = "cache"; |
| cache-size = <65536>; |
| cache-line-size = <64>; |
| cache-sets = <256>; |
| cache-level = <2>; |
| cache-unified; |
| next-level-cache = <&l3_cache>; |
| }; |
| |
| l3_cache: l3-cache { |
| compatible = "cache"; |
| cache-size = <524288>; |
| cache-line-size = <64>; |
| cache-sets = <512>; |
| cache-level = <3>; |
| cache-unified; |
| }; |
| |
| cpu-map { |
| cluster0 { |
| core0 { |
| cpu = <&A55_0>; |
| }; |
| |
| core1 { |
| cpu = <&A55_1>; |
| }; |
| |
| core2 { |
| cpu = <&A55_2>; |
| }; |
| |
| core3 { |
| cpu = <&A55_3>; |
| }; |
| }; |
| }; |
| }; |
| |
| firmware { |
| scmi { |
| compatible = "arm,scmi"; |
| mboxes = <&mu2 5 0>, <&mu2 3 0>, <&mu2 3 1>, <&mu2 5 1>; |
| shmem = <&scmi_buf0>, <&scmi_buf1>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| arm,max-rx-timeout-ms = <5000>; |
| |
| scmi_devpd: protocol@11 { |
| reg = <0x11>; |
| #power-domain-cells = <1>; |
| }; |
| |
| scmi_sys_power: protocol@12 { |
| reg = <0x12>; |
| }; |
| |
| scmi_perf: protocol@13 { |
| reg = <0x13>; |
| #power-domain-cells = <1>; |
| }; |
| |
| scmi_clk: protocol@14 { |
| reg = <0x14>; |
| #clock-cells = <1>; |
| }; |
| |
| scmi_sensor: protocol@15 { |
| reg = <0x15>; |
| #thermal-sensor-cells = <1>; |
| }; |
| |
| scmi_iomuxc: protocol@19 { |
| reg = <0x19>; |
| }; |
| |
| scmi_lmm: protocol@80 { |
| reg = <0x80>; |
| }; |
| |
| scmi_bbm: protocol@81 { |
| reg = <0x81>; |
| }; |
| |
| scmi_cpu: protocol@82 { |
| reg = <0x82>; |
| }; |
| |
| scmi_misc: protocol@84 { |
| reg = <0x84>; |
| }; |
| }; |
| }; |
| |
| gic: interrupt-controller@48000000 { |
| compatible = "arm,gic-v3"; |
| reg = <0 0x48000000 0 0x10000>, |
| <0 0x48060000 0 0xc0000>; |
| interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; |
| interrupt-parent = <&gic>; |
| interrupt-controller; |
| #interrupt-cells = <3>; |
| dma-noncoherent; |
| #address-cells = <2>; |
| #size-cells = <2>; |
| ranges; |
| |
| its: msi-controller@48040000 { |
| compatible = "arm,gic-v3-its"; |
| reg = <0 0x48040000 0 0x20000>; |
| msi-controller; |
| #msi-cells = <1>; |
| dma-noncoherent; |
| }; |
| }; |
| |
| pmu { |
| compatible = "arm,cortex-a55-pmu"; |
| interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; |
| }; |
| |
| psci { |
| compatible = "arm,psci-1.0"; |
| method = "smc"; |
| }; |
| |
| timer { |
| compatible = "arm,armv8-timer"; |
| interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, |
| <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, |
| <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, |
| <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; |
| clock-frequency = <24000000>; |
| arm,no-tick-in-suspend; |
| interrupt-parent = <&gic>; |
| }; |
| |
| usbphynop1: usbphynop1 { |
| compatible = "usb-nop-xceiv"; |
| #phy-cells = <0>; |
| clocks = <&clk_dummy>; |
| clock-names = "main_clk"; |
| }; |
| |
| usbphynop2: usbphynop2 { |
| compatible = "usb-nop-xceiv"; |
| #phy-cells = <0>; |
| clocks = <&clk_dummy>; |
| clock-names = "main_clk"; |
| }; |
| |
| soc { |
| compatible = "simple-bus"; |
| #address-cells = <2>; |
| #size-cells = <2>; |
| ranges = <0x0 0x0 0x0 0x0 0x0 0x80000000>, |
| <0x0 0x28000000 0x0 0x28000000 0x0 0x10000000>; |
| |
| aips2: bus@42000000 { |
| compatible = "fsl,aips-bus", "simple-bus"; |
| reg = <0x0 0x42000000 0x0 0x800000>; |
| ranges = <0x42000000 0x0 0x42000000 0x8000000>, |
| <0x28000000 0x0 0x28000000 0x10000000>; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| |
| mu7: mailbox@42050000 { |
| compatible = "fsl,imx95-mu"; |
| reg = <0x42050000 0x10000>; |
| interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&scmi_clk IMX952_CLK_BUSWAKEUP>; |
| #mbox-cells = <2>; |
| status = "disabled"; |
| }; |
| |
| wdog3: watchdog@420b0000 { |
| compatible = "fsl,imx93-wdt"; |
| reg = <0x420b0000 0x10000>; |
| interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&scmi_clk IMX952_CLK_BUSWAKEUP>; |
| timeout-sec = <40>; |
| status = "disabled"; |
| }; |
| |
| tpm3: pwm@42100000 { |
| compatible = "fsl,imx7ulp-pwm"; |
| reg = <0x42100000 0x1000>; |
| clocks = <&scmi_clk IMX952_CLK_BUSWAKEUP>; |
| #pwm-cells = <3>; |
| status = "disabled"; |
| }; |
| |
| tpm4: pwm@42110000 { |
| compatible = "fsl,imx7ulp-pwm"; |
| reg = <0x42110000 0x1000>; |
| clocks = <&scmi_clk IMX952_CLK_TPM4>; |
| #pwm-cells = <3>; |
| status = "disabled"; |
| }; |
| |
| tpm5: pwm@42120000 { |
| compatible = "fsl,imx7ulp-pwm"; |
| reg = <0x42120000 0x1000>; |
| clocks = <&scmi_clk IMX952_CLK_TPM5>; |
| #pwm-cells = <3>; |
| status = "disabled"; |
| }; |
| |
| tpm6: pwm@42130000 { |
| compatible = "fsl,imx7ulp-pwm"; |
| reg = <0x42130000 0x1000>; |
| clocks = <&scmi_clk IMX952_CLK_TPM6>; |
| #pwm-cells = <3>; |
| status = "disabled"; |
| }; |
| |
| i3c2: i3c@42140000 { |
| compatible = "silvaco,i3c-master-v1"; |
| reg = <0x42140000 0x10000>; |
| interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; |
| #address-cells = <3>; |
| #size-cells = <0>; |
| clocks = <&scmi_clk IMX952_CLK_BUSWAKEUP>, |
| <&scmi_clk IMX952_CLK_I3C2SLOW>, |
| <&clk_dummy>; |
| clock-names = "pclk", "fast_clk", "slow_clk"; |
| status = "disabled"; |
| }; |
| |
| lpi2c3: i2c@42150000 { |
| compatible = "fsl,imx95-lpi2c", "fsl,imx7ulp-lpi2c"; |
| reg = <0x42150000 0x10000>; |
| interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&scmi_clk IMX952_CLK_LPI2C3>, |
| <&scmi_clk IMX952_CLK_BUSWAKEUP>; |
| clock-names = "per", "ipg"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| dmas = <&edma2 8 0 0>, <&edma2 9 0 FSL_EDMA_RX>; |
| dma-names = "tx", "rx"; |
| status = "disabled"; |
| }; |
| |
| lpi2c4: i2c@42160000 { |
| compatible = "fsl,imx95-lpi2c", "fsl,imx7ulp-lpi2c"; |
| reg = <0x42160000 0x10000>; |
| interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&scmi_clk IMX952_CLK_LPI2C4>, |
| <&scmi_clk IMX952_CLK_BUSWAKEUP>; |
| clock-names = "per", "ipg"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| dmas = <&edma2 10 0 0>, <&edma2 11 0 FSL_EDMA_RX>; |
| dma-names = "tx", "rx"; |
| status = "disabled"; |
| }; |
| |
| lpspi3: spi@42170000 { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| compatible = "fsl,imx95-spi", "fsl,imx7ulp-spi"; |
| reg = <0x42170000 0x10000>; |
| interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&scmi_clk IMX952_CLK_LPSPI3>, |
| <&scmi_clk IMX952_CLK_BUSWAKEUP>; |
| clock-names = "per", "ipg"; |
| dmas = <&edma2 12 0 0>, <&edma2 13 0 FSL_EDMA_RX>; |
| dma-names = "tx", "rx"; |
| status = "disabled"; |
| }; |
| |
| lpspi4: spi@42180000 { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| compatible = "fsl,imx95-spi", "fsl,imx7ulp-spi"; |
| reg = <0x42180000 0x10000>; |
| interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&scmi_clk IMX952_CLK_LPSPI4>, |
| <&scmi_clk IMX952_CLK_BUSWAKEUP>; |
| clock-names = "per", "ipg"; |
| dmas = <&edma2 14 0 0>, <&edma2 15 0 FSL_EDMA_RX>; |
| dma-names = "tx", "rx"; |
| status = "disabled"; |
| }; |
| |
| lpuart3: serial@42190000 { |
| compatible = "fsl,imx95-lpuart", "fsl,imx8ulp-lpuart", |
| "fsl,imx7ulp-lpuart"; |
| reg = <0x42190000 0x1000>; |
| interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&scmi_clk IMX952_CLK_LPUART3>; |
| clock-names = "ipg"; |
| dmas = <&edma2 18 0 FSL_EDMA_RX>, <&edma2 17 0 0>; |
| dma-names = "rx", "tx"; |
| status = "disabled"; |
| }; |
| |
| lpuart4: serial@421a0000 { |
| compatible = "fsl,imx95-lpuart", "fsl,imx8ulp-lpuart", |
| "fsl,imx7ulp-lpuart"; |
| reg = <0x421a0000 0x1000>; |
| interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&scmi_clk IMX952_CLK_LPUART4>; |
| clock-names = "ipg"; |
| dmas = <&edma2 20 0 FSL_EDMA_RX>, <&edma2 19 0 0>; |
| dma-names = "rx", "tx"; |
| status = "disabled"; |
| }; |
| |
| lpuart5: serial@421b0000 { |
| compatible = "fsl,imx95-lpuart", "fsl,imx8ulp-lpuart", |
| "fsl,imx7ulp-lpuart"; |
| reg = <0x421b0000 0x1000>; |
| interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&scmi_clk IMX952_CLK_LPUART5>; |
| clock-names = "ipg"; |
| dmas = <&edma2 22 0 FSL_EDMA_RX>, <&edma2 21 0 0>; |
| dma-names = "rx", "tx"; |
| status = "disabled"; |
| }; |
| |
| lpuart6: serial@421c0000 { |
| compatible = "fsl,imx95-lpuart", "fsl,imx8ulp-lpuart", |
| "fsl,imx7ulp-lpuart"; |
| reg = <0x421c0000 0x1000>; |
| interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&scmi_clk IMX952_CLK_LPUART6>; |
| clock-names = "ipg"; |
| dmas = <&edma2 24 0 FSL_EDMA_RX>, <&edma2 23 0 0>; |
| dma-names = "rx", "tx"; |
| status = "disabled"; |
| }; |
| |
| flexcan2: can@421d0000 { |
| compatible = "fsl,imx95-flexcan"; |
| reg = <0x421d0000 0x10000>; |
| interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&scmi_clk IMX952_CLK_BUSWAKEUP>, |
| <&scmi_clk IMX952_CLK_CAN2>; |
| clock-names = "ipg", "per"; |
| assigned-clocks = <&scmi_clk IMX952_CLK_CAN2>; |
| assigned-clock-parents = <&scmi_clk IMX952_CLK_SYSPLL1_PFD1_DIV2>; |
| assigned-clock-rates = <40000000>; |
| fsl,clk-source = /bits/ 8 <0>; |
| status = "disabled"; |
| }; |
| |
| flexcan3: can@42220000 { |
| compatible = "fsl,imx95-flexcan"; |
| reg = <0x42220000 0x10000>; |
| interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&scmi_clk IMX952_CLK_BUSWAKEUP>, |
| <&scmi_clk IMX952_CLK_CAN3>; |
| clock-names = "ipg", "per"; |
| assigned-clocks = <&scmi_clk IMX952_CLK_CAN3>; |
| assigned-clock-parents = <&scmi_clk IMX952_CLK_SYSPLL1_PFD1_DIV2>; |
| assigned-clock-rates = <40000000>; |
| fsl,clk-source = /bits/ 8 <0>; |
| status = "disabled"; |
| }; |
| |
| lpuart7: serial@422b0000 { |
| compatible = "fsl,imx95-lpuart", "fsl,imx8ulp-lpuart", |
| "fsl,imx7ulp-lpuart"; |
| reg = <0x422b0000 0x1000>; |
| interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&scmi_clk IMX952_CLK_LPUART7>; |
| clock-names = "ipg"; |
| dmas = <&edma2 88 0 FSL_EDMA_RX>, <&edma2 87 0 0>; |
| dma-names = "rx", "tx"; |
| status = "disabled"; |
| }; |
| |
| lpuart8: serial@422c0000 { |
| compatible = "fsl,imx95-lpuart", "fsl,imx8ulp-lpuart", |
| "fsl,imx7ulp-lpuart"; |
| reg = <0x422c0000 0x1000>; |
| interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&scmi_clk IMX952_CLK_LPUART8>; |
| clock-names = "ipg"; |
| dmas = <&edma2 90 0 FSL_EDMA_RX>, <&edma2 89 0 0>; |
| dma-names = "rx", "tx"; |
| status = "disabled"; |
| }; |
| |
| lpi2c5: i2c@422d0000 { |
| compatible = "fsl,imx95-lpi2c", "fsl,imx7ulp-lpi2c"; |
| reg = <0x422d0000 0x10000>; |
| interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&scmi_clk IMX952_CLK_LPI2C5>, |
| <&scmi_clk IMX952_CLK_BUSWAKEUP>; |
| clock-names = "per", "ipg"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| dmas = <&edma2 71 0 0>, <&edma2 72 0 FSL_EDMA_RX>; |
| dma-names = "tx", "rx"; |
| status = "disabled"; |
| }; |
| |
| lpi2c6: i2c@422e0000 { |
| compatible = "fsl,imx95-lpi2c", "fsl,imx7ulp-lpi2c"; |
| reg = <0x422e0000 0x10000>; |
| interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&scmi_clk IMX952_CLK_LPI2C6>, |
| <&scmi_clk IMX952_CLK_BUSWAKEUP>; |
| clock-names = "per", "ipg"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| dmas = <&edma2 73 0 0>, <&edma2 74 0 FSL_EDMA_RX>; |
| dma-names = "tx", "rx"; |
| status = "disabled"; |
| }; |
| |
| lpi2c7: i2c@422f0000 { |
| compatible = "fsl,imx95-lpi2c", "fsl,imx7ulp-lpi2c"; |
| reg = <0x422f0000 0x10000>; |
| interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&scmi_clk IMX952_CLK_LPI2C7>, |
| <&scmi_clk IMX952_CLK_BUSWAKEUP>; |
| clock-names = "per", "ipg"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| dmas = <&edma2 75 0 0>, <&edma2 76 0 FSL_EDMA_RX>; |
| dma-names = "tx", "rx"; |
| status = "disabled"; |
| }; |
| |
| lpi2c8: i2c@42300000 { |
| compatible = "fsl,imx95-lpi2c", "fsl,imx7ulp-lpi2c"; |
| reg = <0x42300000 0x10000>; |
| interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&scmi_clk IMX952_CLK_LPI2C8>, |
| <&scmi_clk IMX952_CLK_BUSWAKEUP>; |
| clock-names = "per", "ipg"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| dmas = <&edma2 77 0 0>, <&edma2 78 0 FSL_EDMA_RX>; |
| dma-names = "tx", "rx"; |
| status = "disabled"; |
| }; |
| |
| lpspi5: spi@42310000 { |
| compatible = "fsl,imx95-spi", "fsl,imx7ulp-spi"; |
| reg = <0x42310000 0x10000>; |
| interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| clocks = <&scmi_clk IMX952_CLK_LPSPI5>, |
| <&scmi_clk IMX952_CLK_BUSWAKEUP>; |
| clock-names = "per", "ipg"; |
| dmas = <&edma2 79 0 0>, <&edma2 80 0 FSL_EDMA_RX>; |
| dma-names = "tx", "rx"; |
| status = "disabled"; |
| }; |
| |
| lpspi6: spi@42320000 { |
| compatible = "fsl,imx95-spi", "fsl,imx7ulp-spi"; |
| reg = <0x42320000 0x10000>; |
| interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| clocks = <&scmi_clk IMX952_CLK_LPSPI6>, |
| <&scmi_clk IMX952_CLK_BUSWAKEUP>; |
| clock-names = "per", "ipg"; |
| dmas = <&edma2 81 0 0>, <&edma2 82 0 FSL_EDMA_RX>; |
| dma-names = "tx", "rx"; |
| status = "disabled"; |
| }; |
| |
| lpspi7: spi@42330000 { |
| compatible = "fsl,imx95-spi", "fsl,imx7ulp-spi"; |
| reg = <0x42330000 0x10000>; |
| interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| clocks = <&scmi_clk IMX952_CLK_LPSPI7>, |
| <&scmi_clk IMX952_CLK_BUSWAKEUP>; |
| clock-names = "per", "ipg"; |
| dmas = <&edma2 83 0 0>, <&edma2 84 0 FSL_EDMA_RX>; |
| dma-names = "tx", "rx"; |
| status = "disabled"; |
| }; |
| |
| lpspi8: spi@42340000 { |
| compatible = "fsl,imx95-spi", "fsl,imx7ulp-spi"; |
| reg = <0x42340000 0x10000>; |
| interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| clocks = <&scmi_clk IMX952_CLK_LPSPI8>, |
| <&scmi_clk IMX952_CLK_BUSWAKEUP>; |
| clock-names = "per", "ipg"; |
| dmas = <&edma2 85 0 0>, <&edma2 86 0 FSL_EDMA_RX>; |
| dma-names = "tx", "rx"; |
| status = "disabled"; |
| }; |
| |
| mu8: mailbox@42350000 { |
| compatible = "fsl,imx95-mu"; |
| reg = <0x42350000 0x10000>; |
| interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&scmi_clk IMX952_CLK_BUSWAKEUP>; |
| #mbox-cells = <2>; |
| status = "disabled"; |
| }; |
| |
| xspi1: spi@42400000 { |
| compatible = "nxp,imx952-xspi", "nxp,imx94-xspi"; |
| reg = <0x42400000 0x50000>, <0x28000000 0x8000000>; |
| reg-names = "base", "mmap"; |
| interrupts = <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| clocks = <&scmi_clk IMX952_CLK_XSPI1>; |
| clock-names = "per"; |
| assigned-clocks = <&scmi_clk IMX952_CLK_XSPI1>; |
| assigned-clock-parents = <&scmi_clk IMX952_CLK_SYSPLL1_PFD1>; |
| assigned-clock-rates = <200000000>; |
| status = "disabled"; |
| }; |
| }; |
| |
| aips3: bus@42800000 { |
| compatible = "fsl,aips-bus", "simple-bus"; |
| reg = <0 0x42800000 0 0x800000>; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges = <0x42800000 0x0 0x42800000 0x800000>; |
| |
| edma2: dma-controller@42800000 { |
| compatible = "fsl,imx95-edma5"; |
| reg = <0x42800000 0x210000>; |
| clocks = <&scmi_clk IMX952_CLK_BUSWAKEUP>; |
| clock-names = "dma"; |
| #dma-cells = <3>; |
| dma-channels = <64>; |
| interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; //error irq |
| }; |
| |
| usdhc1: mmc@42c20000 { |
| compatible = "fsl,imx95-usdhc", "fsl,imx8mm-usdhc"; |
| reg = <0x42c20000 0x10000>; |
| interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&scmi_clk IMX952_CLK_BUSWAKEUP>, |
| <&scmi_clk IMX952_CLK_WAKEUPAXI>, |
| <&scmi_clk IMX952_CLK_USDHC1>; |
| clock-names = "ipg", "ahb", "per"; |
| assigned-clocks = <&scmi_clk IMX952_CLK_USDHC1>; |
| assigned-clock-parents = <&scmi_clk IMX952_CLK_SYSPLL1_PFD1>; |
| assigned-clock-rates = <400000000>; |
| bus-width = <8>; |
| fsl,tuning-start-tap = <1>; |
| fsl,tuning-step= <2>; |
| status = "disabled"; |
| }; |
| |
| usdhc2: mmc@42c30000 { |
| compatible = "fsl,imx95-usdhc", "fsl,imx8mm-usdhc"; |
| reg = <0x42c30000 0x10000>; |
| interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&scmi_clk IMX952_CLK_BUSWAKEUP>, |
| <&scmi_clk IMX952_CLK_WAKEUPAXI>, |
| <&scmi_clk IMX952_CLK_USDHC2>; |
| clock-names = "ipg", "ahb", "per"; |
| assigned-clocks = <&scmi_clk IMX952_CLK_USDHC2>; |
| assigned-clock-parents = <&scmi_clk IMX952_CLK_SYSPLL1_PFD1>; |
| assigned-clock-rates = <200000000>; |
| bus-width = <4>; |
| fsl,tuning-start-tap = <1>; |
| fsl,tuning-step= <2>; |
| status = "disabled"; |
| }; |
| |
| usdhc3: mmc@42c40000 { |
| compatible = "fsl,imx95-usdhc", "fsl,imx8mm-usdhc"; |
| reg = <0x42c40000 0x10000>; |
| interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&scmi_clk IMX952_CLK_BUSWAKEUP>, |
| <&scmi_clk IMX952_CLK_WAKEUPAXI>, |
| <&scmi_clk IMX952_CLK_USDHC3>; |
| clock-names = "ipg", "ahb", "per"; |
| bus-width = <4>; |
| fsl,tuning-start-tap = <1>; |
| fsl,tuning-step = <2>; |
| status = "disabled"; |
| }; |
| }; |
| |
| aips5: bus@43000000 { |
| compatible = "fsl,aips-bus", "simple-bus"; |
| reg = <0 0x43000000 0 0x800000>; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges = <0x43000000 0x0 0x43000000 0x800000>; |
| |
| asrc1: asrc@43000000 { |
| compatible = "fsl,imx952-asrc"; |
| reg = <0x43000000 0x10000>; |
| interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&scmi_clk IMX952_CLK_BUSWAKEUP>, |
| <&scmi_clk IMX952_CLK_BUSWAKEUP>, |
| <&scmi_clk IMX952_CLK_ASRC1>, |
| <&scmi_clk IMX952_CLK_ASRC2>, |
| <&clk_dummy>, |
| <&clk_dummy>, |
| <&clk_dummy>, |
| <&clk_dummy>, |
| <&clk_dummy>, |
| <&clk_dummy>, |
| <&clk_dummy>, |
| <&clk_dummy>, |
| <&clk_dummy>, |
| <&clk_dummy>, |
| <&clk_dummy>, |
| <&clk_dummy>, |
| <&clk_dummy>, |
| <&clk_dummy>, |
| <&clk_dummy>; |
| clock-names = "mem", "ipg", |
| "asrck_0", "asrck_1", "asrck_2", "asrck_3", |
| "asrck_4", "asrck_5", "asrck_6", "asrck_7", |
| "asrck_8", "asrck_9", "asrck_a", "asrck_b", |
| "asrck_c", "asrck_d", "asrck_e", "asrck_f", |
| "spba"; |
| dmas = <&edma2 97 0 0>, <&edma2 98 0 0>, <&edma2 99 0 0>, |
| <&edma2 100 0 FSL_EDMA_RX>, <&edma2 101 0 FSL_EDMA_RX>, |
| <&edma2 102 0 FSL_EDMA_RX>; |
| /* tx* is output channel of asrc, it is rx channel for eDMA */ |
| dma-names = "rxa", "rxb", "rxc", |
| "txa", "txb", "txc"; |
| #sound-dai-cells = <0>; |
| fsl,asrc-rate = <8000>; |
| fsl,asrc-width = <16>; |
| status = "disabled"; |
| }; |
| |
| asrc2: asrc@430f0000 { |
| compatible = "fsl,imx952-asrc"; |
| reg = <0x430f0000 0x10000>; |
| interrupts = <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&scmi_clk IMX952_CLK_BUSWAKEUP>, |
| <&scmi_clk IMX952_CLK_BUSWAKEUP>, |
| <&scmi_clk IMX952_CLK_ASRC1>, |
| <&scmi_clk IMX952_CLK_ASRC2>, |
| <&clk_dummy>, |
| <&clk_dummy>, |
| <&clk_dummy>, |
| <&clk_dummy>, |
| <&clk_dummy>, |
| <&clk_dummy>, |
| <&clk_dummy>, |
| <&clk_dummy>, |
| <&clk_dummy>, |
| <&clk_dummy>, |
| <&clk_dummy>, |
| <&clk_dummy>, |
| <&clk_dummy>, |
| <&clk_dummy>, |
| <&clk_dummy>; |
| clock-names = "mem", "ipg", |
| "asrck_0", "asrck_1", "asrck_2", "asrck_3", |
| "asrck_4", "asrck_5", "asrck_6", "asrck_7", |
| "asrck_8", "asrck_9", "asrck_a", "asrck_b", |
| "asrck_c", "asrck_d", "asrck_e", "asrck_f", |
| "spba"; |
| dmas = <&edma2 103 0 0>, <&edma2 104 0 0>, <&edma2 105 0 0>, |
| <&edma2 106 0 FSL_EDMA_RX>, <&edma2 107 0 FSL_EDMA_RX>, |
| <&edma2 108 0 FSL_EDMA_RX>; |
| /* tx* is output channel of asrc, it is rx channel for eDMA */ |
| dma-names = "rxa", "rxb", "rxc", |
| "txa", "txb", "txc"; |
| #sound-dai-cells = <0>; |
| fsl,asrc-rate = <8000>; |
| fsl,asrc-width = <16>; |
| status = "disabled"; |
| }; |
| |
| amix: amix@431f0000 { |
| compatible = "fsl,imx952-audmix"; |
| reg = <0x431f0000 0x10000>; |
| clocks = <&scmi_clk IMX952_CLK_AUDMIX1>; |
| clock-names = "ipg"; |
| status = "disabled"; |
| }; |
| |
| sai3: sai@433e0000 { |
| compatible = "fsl,imx952-sai", "fsl,imx95-sai"; |
| reg = <0x433e0000 0x10000>; |
| interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&scmi_clk IMX952_CLK_BUSWAKEUP>, <&clk_dummy>, |
| <&scmi_clk IMX952_CLK_SAI3>, <&clk_dummy>, |
| <&clk_dummy>; |
| clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; |
| dmas = <&edma2 61 0 FSL_EDMA_RX>, <&edma2 60 0 0>; |
| dma-names = "rx", "tx"; |
| #sound-dai-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| sai4: sai@433f0000 { |
| compatible = "fsl,imx952-sai", "fsl,imx95-sai"; |
| reg = <0x433f0000 0x10000>; |
| interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&scmi_clk IMX952_CLK_BUSWAKEUP>, <&clk_dummy>, |
| <&scmi_clk IMX952_CLK_SAI4>, <&clk_dummy>, |
| <&clk_dummy>; |
| clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; |
| dmas = <&edma2 68 0 FSL_EDMA_RX>, <&edma2 67 0 0>; |
| dma-names = "rx", "tx"; |
| #sound-dai-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| sai5: sai@43400000 { |
| compatible = "fsl,imx952-sai", "fsl,imx95-sai"; |
| reg = <0x43400000 0x10000>; |
| interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&scmi_clk IMX952_CLK_BUSWAKEUP>, <&clk_dummy>, |
| <&scmi_clk IMX952_CLK_SAI5>, <&clk_dummy>, |
| <&clk_dummy>; |
| clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; |
| dmas = <&edma2 70 0 FSL_EDMA_RX>, <&edma2 69 0 0>; |
| dma-names = "rx", "tx"; |
| #sound-dai-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| sai6: sai@43410000 { |
| compatible = "fsl,imx952-sai", "fsl,imx95-sai"; |
| reg = <0x43410000 0x10000>; |
| interrupts = <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&scmi_clk IMX952_CLK_BUSWAKEUP>, <&clk_dummy>, |
| <&scmi_clk IMX952_CLK_SAI3>, <&clk_dummy>, |
| <&clk_dummy>; |
| clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; |
| dmas = <&edma2 96 0 FSL_EDMA_RX>, <&edma2 95 0 0>; |
| dma-names = "rx", "tx"; |
| #sound-dai-cells = <0>; |
| status = "disabled"; |
| }; |
| }; |
| |
| gpio2: gpio@43810000 { |
| compatible = "fsl,imx95-gpio", "fsl,imx8ulp-gpio"; |
| reg = <0x0 0x43810000 0x0 0x1000>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| clocks = <&scmi_clk IMX952_CLK_BUSWAKEUP>, |
| <&scmi_clk IMX952_CLK_BUSWAKEUP>; |
| clock-names = "gpio", "port"; |
| gpio-ranges = <&scmi_iomuxc 0 4 32>; |
| ngpios = <32>; |
| }; |
| |
| gpio3: gpio@43820000 { |
| compatible = "fsl,imx95-gpio", "fsl,imx8ulp-gpio"; |
| reg = <0x0 0x43820000 0x0 0x1000>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| clocks = <&scmi_clk IMX952_CLK_BUSWAKEUP>, |
| <&scmi_clk IMX952_CLK_BUSWAKEUP>; |
| clock-names = "gpio", "port"; |
| gpio-ranges = <&scmi_iomuxc 0 115 8>, <&scmi_iomuxc 8 85 18>, |
| <&scmi_iomuxc 26 53 2>, <&scmi_iomuxc 28 0 4>; |
| ngpios = <32>; |
| }; |
| |
| gpio4: gpio@43840000 { |
| compatible = "fsl,imx95-gpio", "fsl,imx8ulp-gpio"; |
| reg = <0x0 0x43840000 0x0 0x1000>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| clocks = <&scmi_clk IMX952_CLK_BUSWAKEUP>, |
| <&scmi_clk IMX952_CLK_BUSWAKEUP>; |
| clock-names = "gpio", "port"; |
| gpio-ranges = <&scmi_iomuxc 0 57 28>, <&scmi_iomuxc 28 55 2>; |
| ngpios = <30>; |
| }; |
| |
| gpio5: gpio@43850000 { |
| compatible = "fsl,imx95-gpio", "fsl,imx8ulp-gpio"; |
| reg = <0x0 0x43850000 0x0 0x1000>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| clocks = <&scmi_clk IMX952_CLK_BUSWAKEUP>, |
| <&scmi_clk IMX952_CLK_BUSWAKEUP>; |
| clock-names = "gpio", "port"; |
| gpio-ranges = <&scmi_iomuxc 0 103 12>, <&scmi_iomuxc 12 36 6>; |
| ngpios = <18>; |
| }; |
| |
| aips1: bus@44000000 { |
| compatible = "fsl,aips-bus", "simple-bus"; |
| reg = <0x0 0x44000000 0x0 0x800000>; |
| ranges = <0x44000000 0x0 0x44000000 0x800000>; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| |
| edma1: dma-controller@44000000 { |
| compatible = "fsl,imx93-edma3"; |
| reg = <0x44000000 0x210000>; |
| clocks = <&scmi_clk IMX952_CLK_BUSAON>; |
| clock-names = "dma"; |
| #dma-cells = <3>; |
| dma-channels = <32>; |
| interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; //error irq |
| }; |
| |
| mu1: mailbox@44220000 { |
| compatible = "fsl,imx95-mu"; |
| reg = <0x44220000 0x10000>; |
| interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&scmi_clk IMX952_CLK_BUSAON>; |
| #mbox-cells = <2>; |
| status = "disabled"; |
| }; |
| |
| system_counter: timer@44290000 { |
| compatible = "nxp,imx95-sysctr-timer"; |
| reg = <0x44290000 0x30000>; |
| interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&clk_osc_24m>; |
| clock-names = "per"; |
| nxp,no-divider; |
| }; |
| |
| i3c1: i3c@44330000 { |
| compatible = "silvaco,i3c-master-v1"; |
| reg = <0x44330000 0x10000>; |
| interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; |
| #address-cells = <3>; |
| #size-cells = <0>; |
| clocks = <&scmi_clk IMX952_CLK_BUSAON>, |
| <&scmi_clk IMX952_CLK_I3C1SLOW>, |
| <&clk_dummy>; |
| clock-names = "pclk", "fast_clk", "slow_clk"; |
| status = "disabled"; |
| }; |
| |
| lpi2c1: i2c@44340000 { |
| compatible = "fsl,imx95-lpi2c", "fsl,imx7ulp-lpi2c"; |
| reg = <0x44340000 0x10000>; |
| interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&scmi_clk IMX952_CLK_LPI2C1>, |
| <&scmi_clk IMX952_CLK_BUSAON>; |
| clock-names = "per", "ipg"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| dmas = <&edma1 12 0 0>, <&edma1 13 0 FSL_EDMA_RX> ; |
| dma-names = "tx", "rx"; |
| status = "disabled"; |
| }; |
| |
| lpi2c2: i2c@44350000 { |
| compatible = "fsl,imx95-lpi2c", "fsl,imx7ulp-lpi2c"; |
| reg = <0x44350000 0x10000>; |
| interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&scmi_clk IMX952_CLK_LPI2C2>, |
| <&scmi_clk IMX952_CLK_BUSAON>; |
| clock-names = "per", "ipg"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| dmas = <&edma1 14 0 0>, <&edma1 15 0 FSL_EDMA_RX> ; |
| dma-names = "tx", "rx"; |
| status = "disabled"; |
| }; |
| |
| lpspi1: spi@44360000 { |
| compatible = "fsl,imx95-spi", "fsl,imx7ulp-spi"; |
| reg = <0x44360000 0x10000>; |
| interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&scmi_clk IMX952_CLK_LPSPI1>, |
| <&scmi_clk IMX952_CLK_BUSAON>; |
| clock-names = "per", "ipg"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| dmas = <&edma1 16 0 FSL_EDMA_RX>, <&edma1 17 0 0> ; |
| dma-names = "tx", "rx"; |
| status = "disabled"; |
| }; |
| |
| lpspi2: spi@44370000 { |
| compatible = "fsl,imx95-spi", "fsl,imx7ulp-spi"; |
| reg = <0x44370000 0x10000>; |
| interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&scmi_clk IMX952_CLK_LPSPI2>, |
| <&scmi_clk IMX952_CLK_BUSAON>; |
| clock-names = "per", "ipg"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| dmas = <&edma1 18 0 FSL_EDMA_RX>, <&edma1 19 0 0> ; |
| dma-names = "tx", "rx"; |
| status = "disabled"; |
| }; |
| |
| lpuart1: serial@44380000 { |
| compatible = "fsl,imx95-lpuart", "fsl,imx8ulp-lpuart", |
| "fsl,imx7ulp-lpuart"; |
| reg = <0x44380000 0x1000>; |
| interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&scmi_clk IMX952_CLK_LPUART1>; |
| clock-names = "ipg"; |
| dmas = <&edma1 21 0 FSL_EDMA_RX>, <&edma1 20 0 0>; |
| dma-names = "rx", "tx"; |
| status = "disabled"; |
| }; |
| |
| lpuart2: serial@44390000 { |
| compatible = "fsl,imx95-lpuart", "fsl,imx8ulp-lpuart", |
| "fsl,imx7ulp-lpuart"; |
| reg = <0x44390000 0x1000>; |
| interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&scmi_clk IMX952_CLK_LPUART2>; |
| clock-names = "ipg"; |
| dmas = <&edma1 23 0 FSL_EDMA_RX>, <&edma1 22 0 0>; |
| dma-names = "rx", "tx"; |
| status = "disabled"; |
| }; |
| |
| flexcan1: can@443a0000 { |
| compatible = "fsl,imx95-flexcan"; |
| reg = <0x443a0000 0x10000>; |
| interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&scmi_clk IMX952_CLK_BUSAON>, |
| <&scmi_clk IMX952_CLK_CAN1>; |
| clock-names = "ipg", "per"; |
| assigned-clocks = <&scmi_clk IMX952_CLK_CAN1>; |
| assigned-clock-parents = <&scmi_clk IMX952_CLK_SYSPLL1_PFD1_DIV2>; |
| assigned-clock-rates = <40000000>; |
| fsl,clk-source = /bits/ 8 <0>; |
| status = "disabled"; |
| }; |
| |
| sai1: sai@443b0000 { |
| compatible = "fsl,imx952-sai", "fsl,imx95-sai"; |
| reg = <0x443b0000 0x10000>; |
| interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&scmi_clk IMX952_CLK_BUSAON>, <&clk_dummy>, |
| <&scmi_clk IMX952_CLK_SAI1>, <&clk_dummy>, |
| <&clk_dummy>; |
| clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; |
| dmas = <&edma1 25 0 FSL_EDMA_RX>, <&edma1 24 0 0>; |
| dma-names = "rx", "tx"; |
| #sound-dai-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| micfil: micfil@44520000 { |
| compatible = "fsl,imx943-micfil"; |
| reg = <0x44520000 0x10000>; |
| interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&scmi_clk IMX952_CLK_BUSAON>, |
| <&scmi_clk IMX952_CLK_PDM>, |
| <&scmi_clk IMX952_CLK_AUDIOPLL1>, |
| <&scmi_clk IMX952_CLK_AUDIOPLL2>, |
| <&clk_dummy>; |
| clock-names = "ipg_clk", "ipg_clk_app", |
| "pll8k", "pll11k", "clkext3"; |
| dmas = <&edma1 6 0 (FSL_EDMA_MULTI_FIFO | FSL_EDMA_RX)>; |
| dma-names = "rx"; |
| #sound-dai-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| adc1: adc@44530000 { |
| compatible = "nxp,imx93-adc"; |
| reg = <0x44530000 0x10000>; |
| interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&scmi_clk IMX952_CLK_ADC>; |
| clock-names = "ipg"; |
| #io-channel-cells = <1>; |
| status = "disabled"; |
| }; |
| |
| mu2: mailbox@445b0000 { |
| compatible = "fsl,imx95-mu"; |
| reg = <0x445b0000 0x1000>; |
| ranges; |
| interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| #mbox-cells = <2>; |
| |
| sram0: sram@445b1000 { |
| compatible = "mmio-sram"; |
| reg = <0x445b1000 0x400>; |
| ranges = <0x0 0x445b1000 0x400>; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| |
| scmi_buf0: scmi-sram-section@0 { |
| compatible = "arm,scmi-shmem"; |
| reg = <0x0 0x80>; |
| }; |
| |
| scmi_buf1: scmi-sram-section@80 { |
| compatible = "arm,scmi-shmem"; |
| reg = <0x80 0x80>; |
| }; |
| }; |
| |
| }; |
| |
| mu3: mailbox@445d0000 { |
| compatible = "fsl,imx95-mu"; |
| reg = <0x445d0000 0x10000>; |
| interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&scmi_clk IMX952_CLK_BUSAON>; |
| #mbox-cells = <2>; |
| status = "disabled"; |
| }; |
| |
| mu4: mailbox@445f0000 { |
| compatible = "fsl,imx95-mu"; |
| reg = <0x445f0000 0x10000>; |
| interrupts = <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&scmi_clk IMX952_CLK_BUSAON>; |
| #mbox-cells = <2>; |
| status = "disabled"; |
| }; |
| |
| mu5: mailbox@44610000 { |
| compatible = "fsl,imx95-mu"; |
| reg = <0x44610000 0x10000>; |
| interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&scmi_clk IMX952_CLK_BUSAON>; |
| #mbox-cells = <2>; |
| status = "disabled"; |
| }; |
| |
| mu6: mailbox@44630000 { |
| compatible = "fsl,imx95-mu"; |
| reg = <0x44630000 0x10000>; |
| interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&scmi_clk IMX952_CLK_BUSAON>; |
| #mbox-cells = <2>; |
| status = "disabled"; |
| }; |
| }; |
| |
| v2x_mu0: mailbox@47300000 { |
| compatible = "fsl,imx95-mu-v2x"; |
| reg = <0x0 0x47300000 0x0 0x10000>; |
| interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; |
| #mbox-cells = <2>; |
| }; |
| |
| v2x_mu2: mailbox@47320000 { |
| compatible = "fsl,imx95-mu-v2x"; |
| reg = <0x0 0x47320000 0x0 0x10000>; |
| interrupts = <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>; |
| #mbox-cells = <2>; |
| }; |
| |
| v2x_mu3: mailbox@47330000 { |
| compatible = "fsl,imx95-mu-v2x"; |
| reg = <0x0 0x47330000 0x0 0x10000>; |
| interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; |
| #mbox-cells = <2>; |
| }; |
| |
| v2x_mu4: mailbox@47340000 { |
| compatible = "fsl,imx95-mu-v2x"; |
| reg = <0x0 0x47340000 0x0 0x10000>; |
| interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>; |
| #mbox-cells = <2>; |
| }; |
| |
| v2x_mu: mailbox@47350000 { |
| compatible = "fsl,imx95-mu-v2x"; |
| reg = <0x0 0x47350000 0x0 0x10000>; |
| interrupts = <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>; |
| #mbox-cells = <2>; |
| }; |
| |
| /* GPIO1 is under exclusive control of System Manager */ |
| gpio1: gpio@47400000 { |
| compatible = "fsl,imx95-gpio", "fsl,imx8ulp-gpio"; |
| reg = <0x0 0x47400000 0x0 0x1000>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| clocks = <&scmi_clk IMX952_CLK_M33>, |
| <&scmi_clk IMX952_CLK_M33>; |
| clock-names = "gpio", "port"; |
| gpio-ranges = <&scmi_iomuxc 0 123 16>; |
| ngpios = <16>; |
| status = "disabled"; |
| }; |
| |
| elemu0: mailbox@47520000 { |
| compatible = "fsl,imx95-mu-ele"; |
| reg = <0x0 0x47520000 0x0 0x10000>; |
| interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; |
| #mbox-cells = <2>; |
| status = "disabled"; |
| }; |
| |
| elemu1: mailbox@47530000 { |
| compatible = "fsl,imx95-mu-ele"; |
| reg = <0x0 0x47530000 0x0 0x10000>; |
| interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; |
| #mbox-cells = <2>; |
| status = "disabled"; |
| }; |
| |
| elemu2: mailbox@47540000 { |
| compatible = "fsl,imx95-mu-ele"; |
| reg = <0x0 0x47540000 0x0 0x10000>; |
| interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; |
| #mbox-cells = <2>; |
| status = "disabled"; |
| }; |
| |
| elemu3: mailbox@47550000 { |
| compatible = "fsl,imx95-mu-ele"; |
| reg = <0x0 0x47550000 0x0 0x10000>; |
| interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; |
| #mbox-cells = <2>; |
| }; |
| |
| elemu4: mailbox@47560000 { |
| compatible = "fsl,imx95-mu-ele"; |
| reg = <0x0 0x47560000 0x0 0x10000>; |
| interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; |
| #mbox-cells = <2>; |
| status = "disabled"; |
| }; |
| |
| elemu5: mailbox@47570000 { |
| compatible = "fsl,imx95-mu-ele"; |
| reg = <0x0 0x47570000 0x0 0x10000>; |
| interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; |
| #mbox-cells = <2>; |
| status = "disabled"; |
| }; |
| |
| usb1: usb@4c100000 { |
| compatible = "fsl,imx95-usb", "fsl,imx7d-usb", "fsl,imx27-usb"; |
| reg = <0x0 0x4c100000 0x0 0x200>; |
| interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&scmi_clk IMX952_CLK_CGC_HSIOUSB>, |
| <&scmi_clk IMX952_CLK_OSC32K>; |
| clock-names = "usb_ctrl_root", "usb_wakeup"; |
| power-domains = <&scmi_devpd IMX952_PD_HSIO_TOP>; |
| phys = <&usbphynop1>; |
| fsl,usbmisc = <&usbmisc1 0>; |
| status = "disabled"; |
| }; |
| |
| usbmisc1: usbmisc@4c100200 { |
| compatible = "fsl,imx95-usbmisc", "fsl,imx7d-usbmisc", "fsl,imx6q-usbmisc"; |
| #index-cells = <1>; |
| reg = <0x0 0x4c100200 0x0 0x200>, |
| <0x0 0x4c010010 0x0 0x4>; |
| }; |
| |
| usb2: usb@4c200000 { |
| compatible = "fsl,imx95-usb", "fsl,imx7d-usb", "fsl,imx27-usb"; |
| reg = <0x0 0x4c200000 0x0 0x200>; |
| interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&scmi_clk IMX952_CLK_CGC_HSIOUSB>, |
| <&scmi_clk IMX952_CLK_OSC32K>; |
| clock-names = "usb_ctrl_root", "usb_wakeup"; |
| power-domains = <&scmi_devpd IMX952_PD_HSIO_TOP>; |
| phys = <&usbphynop2>; |
| fsl,usbmisc = <&usbmisc2 0>; |
| status = "disabled"; |
| }; |
| |
| usbmisc2: usbmisc@4c200200 { |
| compatible = "fsl,imx95-usbmisc", "fsl,imx7d-usbmisc", "fsl,imx6q-usbmisc"; |
| #index-cells = <1>; |
| reg = <0x0 0x4c200200 0x0 0x200>, |
| <0x0 0x4c010014 0x0 0x4>; |
| }; |
| |
| sai2: sai@4c880000 { |
| compatible = "fsl,imx952-sai", "fsl,imx95-sai"; |
| reg = <0x0 0x4c880000 0x0 0x10000>; |
| interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&scmi_clk IMX952_CLK_BUSNETCMIX>, <&clk_dummy>, |
| <&scmi_clk IMX952_CLK_SAI2>, <&clk_dummy>, |
| <&clk_dummy>; |
| clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; |
| dmas = <&edma2 59 0 FSL_EDMA_RX>, <&edma2 58 0 0>; |
| dma-names = "rx", "tx"; |
| #sound-dai-cells = <0>; |
| power-domains = <&scmi_devpd IMX952_PD_NETC>; |
| status = "disabled"; |
| }; |
| }; |
| }; |
