| // SPDX-License-Identifier: BSD-3-Clause |
| /* |
| * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. |
| */ |
| |
| #include <dt-bindings/interrupt-controller/arm-gic.h> |
| #include <dt-bindings/clock/qcom,ipq5210-gcc.h> |
| #include <dt-bindings/reset/qcom,ipq5210-gcc.h> |
| |
| / { |
| #address-cells = <2>; |
| #size-cells = <2>; |
| interrupt-parent = <&intc>; |
| |
| clocks { |
| sleep_clk: sleep-clk { |
| compatible = "fixed-clock"; |
| #clock-cells = <0>; |
| }; |
| |
| xo_board: xo-board-clk { |
| compatible = "fixed-clock"; |
| #clock-cells = <0>; |
| }; |
| }; |
| |
| cpus { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| cpu@0 { |
| device_type = "cpu"; |
| compatible = "arm,cortex-a53"; |
| reg = <0x0>; |
| enable-method = "psci"; |
| next-level-cache = <&l2_0>; |
| }; |
| |
| cpu@1 { |
| device_type = "cpu"; |
| compatible = "arm,cortex-a53"; |
| reg = <0x1>; |
| enable-method = "psci"; |
| next-level-cache = <&l2_0>; |
| }; |
| |
| cpu@2 { |
| device_type = "cpu"; |
| compatible = "arm,cortex-a53"; |
| reg = <0x2>; |
| enable-method = "psci"; |
| next-level-cache = <&l2_0>; |
| }; |
| |
| cpu@3 { |
| device_type = "cpu"; |
| compatible = "arm,cortex-a53"; |
| reg = <0x3>; |
| enable-method = "psci"; |
| next-level-cache = <&l2_0>; |
| }; |
| |
| l2_0: l2-cache { |
| compatible = "cache"; |
| cache-level = <2>; |
| cache-unified; |
| }; |
| }; |
| |
| firmware { |
| optee { |
| compatible = "linaro,optee-tz"; |
| method = "smc"; |
| }; |
| |
| scm { |
| compatible = "qcom,scm-ipq5210", "qcom,scm"; |
| }; |
| }; |
| |
| memory@80000000 { |
| device_type = "memory"; |
| /* We expect the bootloader to fill in the size */ |
| reg = <0x0 0x80000000 0x0 0x0>; |
| }; |
| |
| pmu { |
| compatible = "arm,cortex-a53-pmu"; |
| interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; |
| }; |
| |
| psci { |
| compatible = "arm,psci-1.0"; |
| method = "smc"; |
| }; |
| |
| reserved-memory { |
| #address-cells = <2>; |
| #size-cells = <2>; |
| ranges; |
| |
| bootloader@87800000 { |
| reg = <0x0 0x87800000 0x0 0x400000>; |
| no-map; |
| }; |
| |
| smem@87c00000 { |
| compatible = "qcom,smem"; |
| reg = <0x0 0x87c00000 0x0 0x40000>; |
| no-map; |
| |
| hwlocks = <&tcsr_mutex 3>; |
| }; |
| |
| tfa@87d00000 { |
| reg = <0x0 0x87d00000 0x0 0x80000>; |
| no-map; |
| }; |
| |
| optee@87d80000 { |
| reg = <0x0 0x87d80000 0x0 0x280000>; |
| no-map; |
| }; |
| }; |
| |
| soc@0 { |
| compatible = "simple-bus"; |
| #address-cells = <2>; |
| #size-cells = <2>; |
| dma-ranges = <0 0 0 0 0x10 0>; |
| ranges = <0 0 0 0 0x10 0>; |
| |
| tlmm: pinctrl@1000000 { |
| compatible = "qcom,ipq5210-tlmm"; |
| reg = <0x0 0x01000000 0x0 0x300000>; |
| interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| gpio-ranges = <&tlmm 0 0 54>; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| }; |
| |
| gcc: clock-controller@1800000 { |
| compatible = "qcom,ipq5210-gcc"; |
| reg = <0x0 0x01800000 0x0 0x40000>; |
| clocks = <&xo_board>, |
| <&sleep_clk>, |
| <0>, |
| <0>, |
| <0>, |
| <0>; |
| #clock-cells = <1>; |
| #reset-cells = <1>; |
| }; |
| |
| tcsr_mutex: hwlock@1905000 { |
| compatible = "qcom,tcsr-mutex"; |
| reg = <0x0 0x01905000 0x0 0x20000>; |
| #hwlock-cells = <1>; |
| }; |
| |
| qupv3: geniqup@1ac0000 { |
| compatible = "qcom,geni-se-qup"; |
| reg = <0x0 0x01ac0000 0x0 0x2000>; |
| clocks = <&gcc GCC_QUPV3_AHB_MST_CLK>, |
| <&gcc GCC_QUPV3_AHB_SLV_CLK>; |
| clock-names = "m-ahb", "s-ahb"; |
| ranges; |
| #address-cells = <2>; |
| #size-cells = <2>; |
| |
| uart1: serial@1a84000 { |
| compatible = "qcom,geni-debug-uart"; |
| reg = <0x0 0x01a84000 0x0 0x4000>; |
| clocks = <&gcc GCC_QUPV3_WRAP_SE1_CLK>; |
| clock-names = "se"; |
| interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; |
| |
| status = "disabled"; |
| }; |
| }; |
| |
| sdhc: mmc@7804000 { |
| compatible = "qcom,ipq5210-sdhci", "qcom,sdhci-msm-v5"; |
| reg = <0x0 0x07804000 0x0 0x1000>, |
| <0x0 0x07805000 0x0 0x1000>; |
| reg-names = "hc", |
| "cqhci"; |
| |
| interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; |
| interrupt-names = "hc_irq", |
| "pwr_irq"; |
| |
| clocks = <&gcc GCC_SDCC1_AHB_CLK>, |
| <&gcc GCC_SDCC1_APPS_CLK>, |
| <&xo_board>; |
| clock-names = "iface", |
| "core", |
| "xo"; |
| non-removable; |
| |
| status = "disabled"; |
| }; |
| |
| intc: interrupt-controller@b000000 { |
| compatible = "qcom,msm-qgic2"; |
| interrupt-controller; |
| #interrupt-cells = <3>; |
| reg = <0x0 0xb000000 0x0 0x1000>, |
| <0x0 0xb002000 0x0 0x1000>, |
| <0x0 0xb001000 0x0 0x1000>, |
| <0x0 0xb004000 0x0 0x1000>; |
| interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; |
| #address-cells = <2>; |
| #size-cells = <2>; |
| ranges = <0 0 0 0x0b00c000 0 0x3000>; |
| |
| v2m0: v2m@0 { |
| compatible = "arm,gic-v2m-frame"; |
| reg = <0x0 0x0 0x0 0xffd>; |
| msi-controller; |
| }; |
| |
| v2m1: v2m@1000 { |
| compatible = "arm,gic-v2m-frame"; |
| reg = <0x0 0x00001000 0x0 0xffd>; |
| msi-controller; |
| }; |
| |
| v2m2: v2m@2000 { |
| compatible = "arm,gic-v2m-frame"; |
| reg = <0x0 0x00002000 0x0 0xffd>; |
| msi-controller; |
| }; |
| }; |
| |
| timer@b120000 { |
| compatible = "arm,armv7-timer-mem"; |
| reg = <0x0 0x0b120000 0x0 0x1000>; |
| ranges = <0 0 0 0x10000000>; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| |
| frame@b121000 { |
| frame-number = <0>; |
| interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; |
| reg = <0x0b121000 0x1000>, |
| <0x0b122000 0x1000>; |
| }; |
| |
| frame@b123000 { |
| frame-number = <1>; |
| interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; |
| reg = <0x0b123000 0x1000>; |
| |
| status = "disabled"; |
| }; |
| |
| frame@b124000 { |
| frame-number = <2>; |
| interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; |
| reg = <0x0b124000 0x1000>; |
| |
| status = "disabled"; |
| }; |
| |
| frame@b125000 { |
| frame-number = <3>; |
| interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; |
| reg = <0x0b125000 0x1000>; |
| |
| status = "disabled"; |
| }; |
| |
| frame@b126000 { |
| frame-number = <4>; |
| interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; |
| reg = <0x0b126000 0x1000>; |
| |
| status = "disabled"; |
| }; |
| |
| frame@b127000 { |
| frame-number = <5>; |
| interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; |
| reg = <0x0b127000 0x1000>; |
| |
| status = "disabled"; |
| }; |
| |
| frame@b128000 { |
| frame-number = <6>; |
| interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; |
| reg = <0x0b128000 0x1000>; |
| |
| status = "disabled"; |
| }; |
| }; |
| }; |
| |
| timer { |
| compatible = "arm,armv8-timer"; |
| interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, |
| <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, |
| <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, |
| <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; |
| }; |
| }; |
