| // SPDX-License-Identifier: BSD-3-Clause |
| /* |
| * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. |
| */ |
| |
| #include <dt-bindings/interrupt-controller/arm-gic.h> |
| #include <dt-bindings/clock/qcom,ipq9650-gcc.h> |
| #include <dt-bindings/reset/qcom,ipq9650-gcc.h> |
| |
| / { |
| #address-cells = <2>; |
| #size-cells = <2>; |
| interrupt-parent = <&intc>; |
| |
| clocks { |
| sleep_clk: sleep-clk { |
| compatible = "fixed-clock"; |
| #clock-cells = <0>; |
| }; |
| |
| xo_board: xo-board-clk { |
| compatible = "fixed-clock"; |
| #clock-cells = <0>; |
| }; |
| }; |
| |
| cpus { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| cpu0: cpu@0 { |
| device_type = "cpu"; |
| compatible = "arm,cortex-a55"; |
| reg = <0x0>; |
| enable-method = "psci"; |
| next-level-cache = <&l2_0>; |
| |
| l2_0: l2-cache { |
| compatible = "cache"; |
| cache-level = <2>; |
| cache-unified; |
| next-level-cache = <&l3_0>; |
| |
| l3_0: l3-cache { |
| compatible = "cache"; |
| cache-level = <3>; |
| cache-unified; |
| }; |
| }; |
| }; |
| |
| cpu1: cpu@100 { |
| device_type = "cpu"; |
| compatible = "arm,cortex-a55"; |
| reg = <0x100>; |
| enable-method = "psci"; |
| next-level-cache = <&l2_100>; |
| |
| l2_100: l2-cache { |
| compatible = "cache"; |
| cache-level = <2>; |
| cache-unified; |
| next-level-cache = <&l3_0>; |
| }; |
| }; |
| |
| cpu2: cpu@200 { |
| device_type = "cpu"; |
| compatible = "arm,cortex-a55"; |
| reg = <0x200>; |
| enable-method = "psci"; |
| |
| l2_200: l2-cache { |
| compatible = "cache"; |
| cache-level = <2>; |
| cache-unified; |
| next-level-cache = <&l3_0>; |
| }; |
| }; |
| |
| cpu3: cpu@300 { |
| device_type = "cpu"; |
| compatible = "arm,cortex-a55"; |
| reg = <0x300>; |
| enable-method = "psci"; |
| |
| l2_300: l2-cache { |
| compatible = "cache"; |
| cache-level = <2>; |
| cache-unified; |
| next-level-cache = <&l3_0>; |
| }; |
| }; |
| |
| cpu4: cpu@400 { |
| device_type = "cpu"; |
| compatible = "arm,cortex-a78"; |
| reg = <0x400>; |
| enable-method = "psci"; |
| next-level-cache = <&l2_400>; |
| |
| l2_400: l2-cache { |
| compatible = "cache"; |
| cache-level = <2>; |
| cache-unified; |
| next-level-cache = <&l3_0>; |
| }; |
| }; |
| |
| cpu-map { |
| cluster0 { |
| core0 { |
| cpu = <&cpu0>; |
| }; |
| |
| core1 { |
| cpu = <&cpu1>; |
| }; |
| |
| core2 { |
| cpu = <&cpu2>; |
| }; |
| |
| core3 { |
| cpu = <&cpu3>; |
| }; |
| |
| core4 { |
| cpu = <&cpu4>; |
| }; |
| }; |
| }; |
| }; |
| |
| firmware { |
| optee { |
| compatible = "linaro,optee-tz"; |
| method = "smc"; |
| }; |
| |
| scm { |
| compatible = "qcom,scm-ipq9650", "qcom,scm"; |
| }; |
| }; |
| |
| memory@80000000 { |
| device_type = "memory"; |
| /* We expect the bootloader to fill in the size */ |
| reg = <0x0 0x80000000 0x0 0x0>; |
| }; |
| |
| pmu-a55 { |
| compatible = "arm,cortex-a55-pmu"; |
| interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster0>; |
| }; |
| |
| pmu-a78 { |
| compatible = "arm,cortex-a78-pmu"; |
| interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster1>; |
| }; |
| |
| psci { |
| compatible = "arm,psci-1.0"; |
| method = "smc"; |
| }; |
| |
| reserved-memory { |
| #address-cells = <2>; |
| #size-cells = <2>; |
| ranges; |
| |
| bootloader@8a100000 { |
| reg = <0x0 0x8a100000 0x0 0x400000>; |
| no-map; |
| }; |
| |
| smem@8a500000 { |
| compatible = "qcom,smem"; |
| reg = <0x0 0x8a500000 0x0 0x40000>; |
| no-map; |
| |
| hwlocks = <&tcsr_mutex 3>; |
| }; |
| |
| tfa@8a600000 { |
| reg = <0x0 0x8a600000 0x0 0x80000>; |
| no-map; |
| }; |
| |
| optee@8a680000 { |
| reg = <0x0 0x8a680000 0x0 0x280000>; |
| no-map; |
| }; |
| }; |
| |
| soc@0 { |
| compatible = "simple-bus"; |
| #address-cells = <2>; |
| #size-cells = <2>; |
| dma-ranges = <0 0 0 0 0x10 0>; |
| ranges = <0 0 0 0 0x10 0>; |
| |
| tlmm: pinctrl@1000000 { |
| compatible = "qcom,ipq9650-tlmm"; |
| reg = <0x0 0x01000000 0x0 0x300000>; |
| interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH 0>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| gpio-ranges = <&tlmm 0 0 54>; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| }; |
| |
| gcc: clock-controller@1800000 { |
| compatible = "qcom,ipq9650-gcc"; |
| reg = <0x0 0x01800000 0x0 0x40000>; |
| clocks = <&xo_board>, |
| <&sleep_clk>, |
| <0>, |
| <0>, |
| <0>, |
| <0>, |
| <0>, |
| <0>, |
| <0>; |
| #clock-cells = <1>; |
| #reset-cells = <1>; |
| }; |
| |
| tcsr_mutex: hwlock@1917000 { |
| compatible = "qcom,tcsr-mutex"; |
| reg = <0x0 0x01917000 0x0 0x57000>; |
| #hwlock-cells = <1>; |
| }; |
| |
| qupv3: geniqup@1ac0000 { |
| compatible = "qcom,geni-se-qup"; |
| reg = <0x0 0x01ac0000 0x0 0x2000>; |
| clocks = <&gcc GCC_QUPV3_AHB_MST_CLK>, |
| <&gcc GCC_QUPV3_AHB_SLV_CLK>; |
| clock-names = "m-ahb", "s-ahb"; |
| #address-cells = <2>; |
| #size-cells = <2>; |
| ranges; |
| |
| uart1: serial@1a98000 { |
| compatible = "qcom,geni-debug-uart"; |
| reg = <0x0 0x01a98000 0x0 0x4000>; |
| clocks = <&gcc GCC_QUPV3_WRAP_SE6_CLK>; |
| clock-names = "se"; |
| interrupts = <GIC_SPI 380 IRQ_TYPE_LEVEL_HIGH 0>; |
| |
| status = "disabled"; |
| }; |
| }; |
| |
| sdhc: mmc@7804000 { |
| compatible = "qcom,ipq9650-sdhci", "qcom,sdhci-msm-v5"; |
| reg = <0x0 0x07804000 0x0 0x1000>, |
| <0x0 0x07805000 0x0 0x1000>; |
| reg-names = "hc", |
| "cqhci"; |
| |
| interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH 0>, |
| <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>; |
| interrupt-names = "hc_irq", |
| "pwr_irq"; |
| |
| clocks = <&gcc GCC_SDCC1_AHB_CLK>, |
| <&gcc GCC_SDCC1_APPS_CLK>, |
| <&xo_board>; |
| clock-names = "iface", |
| "core", |
| "xo"; |
| non-removable; |
| |
| status = "disabled"; |
| }; |
| |
| intc: interrupt-controller@f200000 { |
| compatible = "arm,gic-v3"; |
| reg = <0x0 0x0f200000 0x0 0x10000>, |
| <0x0 0x0f240000 0x0 0xa0000>; |
| #interrupt-cells = <0x4>; |
| interrupt-controller; |
| #redistributor-regions = <1>; |
| redistributor-stride = <0x0 0x20000>; |
| interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>; |
| mbi-ranges = <800 160>; |
| msi-controller; |
| |
| ppi-partitions { |
| ppi_cluster0: interrupt-partition-0 { |
| affinity = <&cpu0 &cpu1 &cpu2 &cpu3>; |
| }; |
| |
| ppi_cluster1: interrupt-partition-1 { |
| affinity = <&cpu4>; |
| }; |
| }; |
| }; |
| |
| watchdog@f410000 { |
| compatible = "qcom,apss-wdt-ipq9650", "qcom,kpss-wdt"; |
| reg = <0x0 0x0f410000 0x0 0x1000>; |
| interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING 0>; |
| clocks = <&sleep_clk>; |
| }; |
| |
| timer@f420000 { |
| compatible = "arm,armv7-timer-mem"; |
| reg = <0x0 0x0f420000 0x0 0x1000>; |
| ranges = <0 0 0 0x10000000>; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| |
| frame@f421000 { |
| reg = <0x0f421000 0x1000>, |
| <0x0f422000 0x1000>; |
| interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH 0>, |
| <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH 0>; |
| frame-number = <0>; |
| }; |
| |
| frame@f423000 { |
| reg = <0x0f423000 0x1000>; |
| interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH 0>; |
| frame-number = <1>; |
| |
| status = "disabled"; |
| }; |
| |
| frame@f425000 { |
| reg = <0x0f425000 0x1000>, |
| <0x0f426000 0x1000>; |
| interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH 0>; |
| frame-number = <2>; |
| |
| status = "disabled"; |
| }; |
| |
| frame@f427000 { |
| reg = <0x0f427000 0x1000>; |
| interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH 0>; |
| frame-number = <3>; |
| |
| status = "disabled"; |
| }; |
| |
| frame@f429000 { |
| reg = <0x0f429000 0x1000>; |
| interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH 0>; |
| frame-number = <4>; |
| |
| status = "disabled"; |
| }; |
| |
| frame@f42b000 { |
| reg = <0x0f42b000 0x1000>; |
| interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH 0>; |
| frame-number = <5>; |
| |
| status = "disabled"; |
| }; |
| |
| frame@f42d000 { |
| reg = <0x0f42d000 0x1000>; |
| interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH 0>; |
| frame-number = <6>; |
| |
| status = "disabled"; |
| }; |
| }; |
| }; |
| |
| timer { |
| compatible = "arm,armv8-timer"; |
| interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0>, |
| <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0>, |
| <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW 0>, |
| <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>, |
| <GIC_PPI 12 IRQ_TYPE_LEVEL_LOW 0>; |
| }; |
| }; |
