| // SPDX-License-Identifier: BSD-3-Clause |
| /* |
| * Copyright (c) 2025, Qualcomm Innovation Center, Inc. All rights reserved. |
| */ |
| |
| /dts-v1/; |
| /plugin/; |
| #include <dt-bindings/gpio/gpio.h> |
| #include <dt-bindings/clock/qcom,gcc-sc7280.h> |
| #include <dt-bindings/pinctrl/qcom,pmic-gpio.h> |
| |
| &{/} { |
| |
| vreg_0p9: regulator-0v9 { |
| compatible = "regulator-fixed"; |
| regulator-name = "VREG_0P9"; |
| regulator-min-microvolt = <900000>; |
| regulator-max-microvolt = <900000>; |
| |
| regulator-always-on; |
| regulator-boot-on; |
| }; |
| |
| vreg_1p8: regulator-1v8 { |
| compatible = "regulator-fixed"; |
| regulator-name = "VREG_1P8"; |
| regulator-min-microvolt = <1800000>; |
| regulator-max-microvolt = <1800000>; |
| |
| regulator-always-on; |
| regulator-boot-on; |
| }; |
| }; |
| |
| &remoteproc_wpss { |
| status = "disabled"; |
| }; |
| |
| &spi11 { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "okay"; |
| |
| st33htpm0: tpm@0 { |
| compatible = "st,st33htpm-spi", "tcg,tpm_tis-spi"; |
| reg = <0>; |
| spi-max-frequency = <20000000>; |
| }; |
| }; |
| |
| &pcie0 { |
| perst-gpios = <&tlmm 87 GPIO_ACTIVE_LOW>; |
| |
| pinctrl-0 = <&pcie0_reset_n>, <&pcie0_wake_n>, <&pcie0_clkreq_n>; |
| pinctrl-names = "default"; |
| |
| iommu-map = <0x0 &apps_smmu 0x1c00 0x1>, |
| <0x100 &apps_smmu 0x1c01 0x1>, |
| <0x208 &apps_smmu 0x1c04 0x1>, |
| <0x210 &apps_smmu 0x1c05 0x1>, |
| <0x218 &apps_smmu 0x1c06 0x1>, |
| <0x300 &apps_smmu 0x1c07 0x1>, |
| <0x400 &apps_smmu 0x1c08 0x1>, |
| <0x500 &apps_smmu 0x1c09 0x1>, |
| <0x501 &apps_smmu 0x1c10 0x1>; |
| |
| status = "okay"; |
| }; |
| |
| &pcie0_phy { |
| vdda-phy-supply = <&vreg_l10c_0p88>; |
| vdda-pll-supply = <&vreg_l6b_1p2>; |
| |
| status = "okay"; |
| }; |
| |
| &pcie0_port { |
| #address-cells = <3>; |
| #size-cells = <2>; |
| |
| pcie@0,0 { |
| compatible = "pci1179,0623"; |
| reg = <0x10000 0x0 0x0 0x0 0x0>; |
| #address-cells = <3>; |
| #size-cells = <2>; |
| |
| device_type = "pci"; |
| ranges; |
| bus-range = <0x2 0xff>; |
| |
| vddc-supply = <&vreg_0p9>; |
| vdd18-supply = <&vreg_1p8>; |
| vdd09-supply = <&vreg_0p9>; |
| vddio1-supply = <&vreg_1p8>; |
| vddio2-supply = <&vreg_1p8>; |
| vddio18-supply = <&vreg_1p8>; |
| |
| i2c-parent = <&i2c1 0x33>; |
| |
| resx-gpios = <&tlmm 78 GPIO_ACTIVE_LOW>; |
| |
| pinctrl-0 = <&pcie0_tc9563_resx_n>; |
| pinctrl-names = "default"; |
| |
| pcie@1,0 { |
| reg = <0x20800 0x0 0x0 0x0 0x0>; |
| #address-cells = <3>; |
| #size-cells = <2>; |
| |
| device_type = "pci"; |
| ranges; |
| bus-range = <0x3 0xff>; |
| }; |
| |
| pcie@2,0 { |
| reg = <0x21000 0x0 0x0 0x0 0x0>; |
| #address-cells = <3>; |
| #size-cells = <2>; |
| |
| device_type = "pci"; |
| ranges; |
| bus-range = <0x4 0xff>; |
| }; |
| |
| pcie@3,0 { |
| reg = <0x21800 0x0 0x0 0x0 0x0>; |
| #address-cells = <3>; |
| #size-cells = <2>; |
| device_type = "pci"; |
| ranges; |
| bus-range = <0x5 0xff>; |
| |
| pci@0,0 { |
| reg = <0x50000 0x0 0x0 0x0 0x0>; |
| #address-cells = <3>; |
| #size-cells = <2>; |
| device_type = "pci"; |
| ranges; |
| }; |
| |
| pci@0,1 { |
| reg = <0x50100 0x0 0x0 0x0 0x0>; |
| #address-cells = <3>; |
| #size-cells = <2>; |
| device_type = "pci"; |
| ranges; |
| }; |
| }; |
| |
| }; |
| }; |
| |
| &pcie1 { |
| iommu-map = <0x0 &apps_smmu 0x1c80 0x1>, |
| <0x100 &apps_smmu 0x1c81 0x1>, |
| <0x208 &apps_smmu 0x1c84 0x1>, |
| <0x210 &apps_smmu 0x1c85 0x1>, |
| <0x218 &apps_smmu 0x1c86 0x1>, |
| <0x300 &apps_smmu 0x1c87 0x1>, |
| <0x408 &apps_smmu 0x1c90 0x1>, |
| <0x410 &apps_smmu 0x1c91 0x1>, |
| <0x418 &apps_smmu 0x1c92 0x1>, |
| <0x500 &apps_smmu 0x1c93 0x1>, |
| <0x600 &apps_smmu 0x1c94 0x1>, |
| <0x700 &apps_smmu 0x1c95 0x1>, |
| <0x701 &apps_smmu 0x1c96 0x1>, |
| <0x800 &apps_smmu 0x1c97 0x1>, |
| <0x900 &apps_smmu 0x1c98 0x1>, |
| <0x901 &apps_smmu 0x1c99 0x1>; |
| }; |
| |
| &pcie1_switch0_dsp1 { |
| #address-cells = <3>; |
| #size-cells = <2>; |
| |
| pcie@0,0 { |
| compatible = "pci1179,0623"; |
| reg = <0x30000 0x0 0x0 0x0 0x0>; |
| #address-cells = <3>; |
| #size-cells = <2>; |
| |
| device_type = "pci"; |
| ranges; |
| bus-range = <0x2 0xff>; |
| |
| vddc-supply = <&vdd_ntn_0p9>; |
| vdd18-supply = <&vdd_ntn_1p8>; |
| vdd09-supply = <&vdd_ntn_0p9>; |
| vddio1-supply = <&vdd_ntn_1p8>; |
| vddio2-supply = <&vdd_ntn_1p8>; |
| vddio18-supply = <&vdd_ntn_1p8>; |
| |
| i2c-parent = <&i2c1 0x77>; |
| |
| resx-gpios = <&tlmm 124 GPIO_ACTIVE_LOW>; |
| |
| pinctrl-0 = <&pcie1_tc9563_resx_n>; |
| pinctrl-names = "default"; |
| |
| pcie@1,0 { |
| reg = <0x40800 0x0 0x0 0x0 0x0>; |
| #address-cells = <3>; |
| #size-cells = <2>; |
| |
| device_type = "pci"; |
| ranges; |
| bus-range = <0x3 0xff>; |
| }; |
| |
| pcie@2,0 { |
| reg = <0x41000 0x0 0x0 0x0 0x0>; |
| #address-cells = <3>; |
| #size-cells = <2>; |
| |
| device_type = "pci"; |
| ranges; |
| bus-range = <0x4 0xff>; |
| }; |
| |
| pcie@3,0 { |
| reg = <0x41800 0x0 0x0 0x0 0x0>; |
| #address-cells = <3>; |
| #size-cells = <2>; |
| device_type = "pci"; |
| ranges; |
| bus-range = <0x5 0xff>; |
| |
| pci@0,0 { |
| reg = <0x50000 0x0 0x0 0x0 0x0>; |
| #address-cells = <3>; |
| #size-cells = <2>; |
| device_type = "pci"; |
| ranges; |
| }; |
| |
| pci@0,1 { |
| reg = <0x50100 0x0 0x0 0x0 0x0>; |
| #address-cells = <3>; |
| #size-cells = <2>; |
| device_type = "pci"; |
| ranges; |
| }; |
| }; |
| }; |
| }; |
| |
| &tlmm { |
| pcie0_tc9563_resx_n: pcie0-tc9563-resx-state { |
| pins = "gpio78"; |
| function = "gpio"; |
| bias-disable; |
| input-disable; |
| output-enable; |
| }; |
| |
| pcie0_reset_n: pcie0-reset-n-state { |
| pins = "gpio87"; |
| function = "gpio"; |
| drive-strength = <16>; |
| output-low; |
| bias-disable; |
| }; |
| |
| pcie0_clkreq_n: pcie0-clkreq-n-state { |
| pins = "gpio88"; |
| function = "pcie0_clkreqn"; |
| drive-strength = <2>; |
| bias-pull-up; |
| }; |
| |
| pcie0_wake_n: pcie0-wake-n-state { |
| pins = "gpio89"; |
| function = "gpio"; |
| drive-strength = <2>; |
| bias-pull-up; |
| }; |
| |
| pcie1_tc9563_resx_n: pcie1-tc9563-resx-state { |
| pins = "gpio124"; |
| function = "gpio"; |
| bias-disable; |
| input-disable; |
| output-enable; |
| }; |
| |
| }; |
| |
| &wifi { |
| status = "disabled"; |
| }; |
