arch/arm64/boot/dts/renesas/r9a07g044l2-remi-pi.dts - linux - Git at Google

 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
 /*
  * Device Tree Source for the MYIR Remi Pi
  *
  * Copyright (C) 2022 MYIR Electronics Corp.
  * Copyright (C) 2025 Collabora Ltd.
  */

 /dts-v1/;

 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/pinctrl/rzg2l-pinctrl.h>

 #include "r9a07g044l2.dtsi"

 / {
 	model = "MYIR Tech Limited Remi Pi MYB-YG2LX-REMI";
 	compatible = "myir,remi-pi", "renesas,r9a07g044l2", "renesas,r9a07g044";

 	aliases {
 		ethernet0 = &eth0;
 		ethernet1 = &eth1;

 		i2c0 = &i2c0;
 		i2c1 = &i2c1;
 		i2c2 = &i2c2;
 		i2c3 = &i2c3;

 		mmc0 = &sdhi0;

 		serial0 = &scif0;
 		serial4 = &scif4;
 	};

 	chosen {
 		stdout-path = "serial0:115200n8";
 	};

 	hdmi-out {
 		compatible = "hdmi-connector";
 		type = "a";
 		ddc-i2c-bus = <&i2c1>;

 		port {
 			hdmi_con: endpoint {
 				remote-endpoint = <&lt8912_out>;
 			};
 		};
 	};

 	memory@48000000 {
 		device_type = "memory";
 		/* first 128MB is reserved for secure area. */
 		reg = <0x0 0x48000000 0x0 0x38000000>;
 	};

 	reg_1p8v: regulator-1p8v {
 		compatible = "regulator-fixed";
 		regulator-name = "fixed-1.8V";
 		vin-supply = <&reg_5p0v>;
 		regulator-min-microvolt = <1800000>;
 		regulator-max-microvolt = <1800000>;
 		regulator-always-on;
 	};

 	reg_3p3v: regulator-3p3v {
 		compatible = "regulator-fixed";
 		regulator-name = "fixed-3.3V";
 		vin-supply = <&reg_5p0v>;
 		regulator-min-microvolt = <3300000>;
 		regulator-max-microvolt = <3300000>;
 		regulator-always-on;
 	};

 	reg_5p0v: regulator-5p0v {
 		compatible = "regulator-fixed";
 		regulator-name = "fixed-5.0V";
 		regulator-min-microvolt = <5000000>;
 		regulator-max-microvolt = <5000000>;
 	};

 	reg_1p1v: regulator-vdd-core {
 		compatible = "regulator-fixed";
 		regulator-name = "fixed-1.1V";
 		regulator-min-microvolt = <1100000>;
 		regulator-max-microvolt = <1100000>;
 		regulator-always-on;
 	};
 };

 &dsi {
 	status = "okay";

 	ports {
 		port@1 {
 			dsi_out: endpoint {
 				remote-endpoint = <&lt8912_in>;
 				data-lanes = <1 2 3 4>;
 			};
 		};
 	};
 };

 &du {
 	status = "okay";
 };

 &ehci1 {
 	status = "okay";
 };

 &eth0 {
 	pinctrl-0 = <&eth0_pins>;
 	pinctrl-names = "default";
 	phy-handle = <&phy0>;
 	phy-mode = "rgmii-id";
 	status = "okay";

 	phy0: ethernet-phy@4 {
 		compatible = "ethernet-phy-ieee802.3-c22";
 		reg = <4>;
 		interrupts-extended = <&pinctrl RZG2L_GPIO(44, 2) IRQ_TYPE_LEVEL_LOW>;
 		reset-gpios = <&pinctrl RZG2L_GPIO(44, 3) GPIO_ACTIVE_LOW>;
 	};
 };

 &eth1 {
 	pinctrl-0 = <&eth1_pins>;
 	pinctrl-names = "default";
 	phy-handle = <&phy1>;
 	phy-mode = "rgmii-id";
 	status = "okay";

 	phy1: ethernet-phy@6 {
 		compatible = "ethernet-phy-ieee802.3-c22";
 		reg = <6>;
 		interrupts-extended = <&pinctrl RZG2L_GPIO(43, 2) IRQ_TYPE_LEVEL_LOW>;
 		reset-gpios = <&pinctrl RZG2L_GPIO(43, 3) GPIO_ACTIVE_LOW>;
 	};
 };

 &extal_clk {
 	clock-frequency = <24000000>;
 };

 &gpu {
 	mali-supply = <&reg_1p1v>;
 };

 &i2c0 {
 	pinctrl-0 = <&i2c0_pins>;
 	pinctrl-names = "default";

 	clock-frequency = <400000>;
 	status = "okay";

 	hdmi-bridge@48 {
 		compatible = "lontium,lt8912b";
 		reg = <0x48> ;
 		reset-gpios = <&pinctrl RZG2L_GPIO(42, 2) GPIO_ACTIVE_LOW>;

 		ports {
 			#address-cells = <1>;
 			#size-cells = <0>;

 			port@0 {
 				reg = <0>;

 				lt8912_in: endpoint {
 					data-lanes = <1 2 3 4>;
 					remote-endpoint = <&dsi_out>;
 				};
 			};

 			port@1 {
 				reg = <1>;

 				lt8912_out: endpoint {
 					remote-endpoint = <&hdmi_con>;
 				};
 			};
 		};
 	};
 };

 &i2c1 {
 	pinctrl-0 = <&i2c1_pins>;
 	pinctrl-names = "default";
 	clock-frequency = <100000>;
 	status = "okay";
 };

 &i2c2 {
 	pinctrl-0 = <&i2c2_pins>;
 	pinctrl-names = "default";
 	clock-frequency = <100000>;
 	status = "okay";
 };

 &i2c3 {
 	pinctrl-0 = <&i2c3_pins>;
 	pinctrl-names = "default";
 	clock-frequency = <100000>;
 	status = "okay";
 };

 &mtu3 {
 	status = "okay";
 };

 &ohci1 {
 	status = "okay";
 };

 &ostm1 {
 	status = "okay";
 };

 &ostm2 {
 	status = "okay";
 };

 &phyrst {
 	status = "okay";
 };

 &pinctrl {
 	eth0_pins: eth0 {
 		pinmux = <RZG2L_PORT_PINMUX(27, 1, 1)>, /* ET0_MDC */
 			 <RZG2L_PORT_PINMUX(28, 0, 1)>, /* ET0_MDIO */
 			 <RZG2L_PORT_PINMUX(20, 0, 1)>, /* ET0_TXC */
 			 <RZG2L_PORT_PINMUX(20, 1, 1)>, /* ET0_TX_CTL */
 			 <RZG2L_PORT_PINMUX(20, 2, 1)>, /* ET0_TXD0 */
 			 <RZG2L_PORT_PINMUX(21, 0, 1)>, /* ET0_TXD1 */
 			 <RZG2L_PORT_PINMUX(21, 1, 1)>, /* ET0_TXD2 */
 			 <RZG2L_PORT_PINMUX(22, 0, 1)>, /* ET0_TXD3 */
 			 <RZG2L_PORT_PINMUX(24, 0, 1)>, /* ET0_RXC */
 			 <RZG2L_PORT_PINMUX(24, 1, 1)>, /* ET0_RX_CTL */
 			 <RZG2L_PORT_PINMUX(25, 0, 1)>, /* ET0_RXD0 */
 			 <RZG2L_PORT_PINMUX(25, 1, 1)>, /* ET0_RXD1 */
 			 <RZG2L_PORT_PINMUX(26, 0, 1)>, /* ET0_RXD2 */
 			 <RZG2L_PORT_PINMUX(26, 1, 1)>; /* ET0_RXD3 */
 	};

 	eth1_pins: eth1 {
 		pinmux = <RZG2L_PORT_PINMUX(37, 0, 1)>, /* ET1_MDC */
 			 <RZG2L_PORT_PINMUX(37, 1, 1)>, /* ET1_MDIO */
 			 <RZG2L_PORT_PINMUX(29, 0, 1)>, /* ET1_TXC */
 			 <RZG2L_PORT_PINMUX(29, 1, 1)>, /* ET1_TX_CTL */
 			 <RZG2L_PORT_PINMUX(30, 0, 1)>, /* ET1_TXD0 */
 			 <RZG2L_PORT_PINMUX(30, 1, 1)>, /* ET1_TXD1 */
 			 <RZG2L_PORT_PINMUX(31, 0, 1)>, /* ET1_TXD2 */
 			 <RZG2L_PORT_PINMUX(31, 1, 1)>, /* ET1_TXD3 */
 			 <RZG2L_PORT_PINMUX(33, 1, 1)>, /* ET1_RXC */
 			 <RZG2L_PORT_PINMUX(34, 0, 1)>, /* ET1_RX_CTL */
 			 <RZG2L_PORT_PINMUX(34, 1, 1)>, /* ET1_RXD0 */
 			 <RZG2L_PORT_PINMUX(35, 0, 1)>, /* ET1_RXD1 */
 			 <RZG2L_PORT_PINMUX(35, 1, 1)>, /* ET1_RXD2 */
 			 <RZG2L_PORT_PINMUX(36, 0, 1)>; /* ET1_RXD3 */
 	};

 	i2c0_pins: i2c0 {
 		pins = "RIIC0_SDA", "RIIC0_SCL";
 		input-enable;
 	};

 	i2c1_pins: i2c1 {
 		pins = "RIIC1_SDA", "RIIC1_SCL";
 		input-enable;
 	};

 	i2c2_pins: i2c2 {
 		pinmux = <RZG2L_PORT_PINMUX(3, 0, 2)>, /* SDA */
 			 <RZG2L_PORT_PINMUX(3, 1, 2)>; /* SCL */
 	};

 	i2c3_pins: i2c3 {
 		pinmux = <RZG2L_PORT_PINMUX(18, 0, 3)>, /* SDA */
 			 <RZG2L_PORT_PINMUX(18, 1, 3)>; /* SCL */
 	};

 	scif0_pins: scif0 {
 		pinmux = <RZG2L_PORT_PINMUX(38, 0, 1)>, /* TxD */
 			 <RZG2L_PORT_PINMUX(38, 1, 1)>; /* RxD */
 	};

 	scif4_pins: scif4 {
 		pinmux = <RZG2L_PORT_PINMUX(2, 0, 5)>, /* TxD */
 			 <RZG2L_PORT_PINMUX(2, 1, 5)>; /* RxD */
 	};

 	sdhi0_pins: sd0 {
 		sd0-ctrl {
 			pins = "SD0_CLK", "SD0_CMD";
 			power-source = <1800>;
 		};

 		sd0-data {
 			pins = "SD0_DATA0", "SD0_DATA1", "SD0_DATA2", "SD0_DATA3",
 			       "SD0_DATA4", "SD0_DATA5", "SD0_DATA6", "SD0_DATA7";
 			power-source = <1800>;
 		};

 		sd0-rst {
 			pins = "SD0_RST#";
 			power-source = <1800>;
 		};
 	};
 };

 &scif0 {
 	pinctrl-0 = <&scif0_pins>;
 	pinctrl-names = "default";
 	status = "okay";
 };

 &scif4 {
 	pinctrl-0 = <&scif4_pins>;
 	pinctrl-names = "default";
 	status = "okay";
 };

 &sdhi0 {
 	pinctrl-0 = <&sdhi0_pins>;
 	pinctrl-1 = <&sdhi0_pins>;
 	pinctrl-names = "default", "state_uhs";

 	vmmc-supply = <&reg_3p3v>;
 	vqmmc-supply = <&reg_1p8v>;
 	bus-width = <8>;
 	mmc-hs200-1_8v;
 	non-removable;
 	fixed-emmc-driver-type = <1>;
 	status = "okay";
 };

 &usb2_phy1 {
 	status = "okay";
 };
	// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
	/*
	* Device Tree Source for the MYIR Remi Pi
	*
	* Copyright (C) 2022 MYIR Electronics Corp.
	* Copyright (C) 2025 Collabora Ltd.
	*/

	/dts-v1/;

	#include <dt-bindings/gpio/gpio.h>
	#include <dt-bindings/pinctrl/rzg2l-pinctrl.h>

	#include "r9a07g044l2.dtsi"

	/ {
	model = "MYIR Tech Limited Remi Pi MYB-YG2LX-REMI";
	compatible = "myir,remi-pi", "renesas,r9a07g044l2", "renesas,r9a07g044";

	aliases {
	ethernet0 = &eth0;
	ethernet1 = &eth1;

	i2c0 = &i2c0;
	i2c1 = &i2c1;
	i2c2 = &i2c2;
	i2c3 = &i2c3;

	mmc0 = &sdhi0;

	serial0 = &scif0;
	serial4 = &scif4;
	};

	chosen {
	stdout-path = "serial0:115200n8";
	};

	hdmi-out {
	compatible = "hdmi-connector";
	type = "a";
	ddc-i2c-bus = <&i2c1>;

	port {
	hdmi_con: endpoint {
	remote-endpoint = <&lt8912_out>;
	};
	};
	};

	memory@48000000 {
	device_type = "memory";
	/* first 128MB is reserved for secure area. */
	reg = <0x0 0x48000000 0x0 0x38000000>;
	};

	reg_1p8v: regulator-1p8v {
	compatible = "regulator-fixed";
	regulator-name = "fixed-1.8V";
	vin-supply = <&reg_5p0v>;
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	regulator-always-on;
	};

	reg_3p3v: regulator-3p3v {
	compatible = "regulator-fixed";
	regulator-name = "fixed-3.3V";
	vin-supply = <&reg_5p0v>;
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	regulator-always-on;
	};

	reg_5p0v: regulator-5p0v {
	compatible = "regulator-fixed";
	regulator-name = "fixed-5.0V";
	regulator-min-microvolt = <5000000>;
	regulator-max-microvolt = <5000000>;
	};

	reg_1p1v: regulator-vdd-core {
	compatible = "regulator-fixed";
	regulator-name = "fixed-1.1V";
	regulator-min-microvolt = <1100000>;
	regulator-max-microvolt = <1100000>;
	regulator-always-on;
	};
	};

	&dsi {
	status = "okay";

	ports {
	port@1 {
	dsi_out: endpoint {
	remote-endpoint = <&lt8912_in>;
	data-lanes = <1 2 3 4>;
	};
	};
	};
	};

	&du {
	status = "okay";
	};

	&ehci1 {
	status = "okay";
	};

	&eth0 {
	pinctrl-0 = <&eth0_pins>;
	pinctrl-names = "default";
	phy-handle = <&phy0>;
	phy-mode = "rgmii-id";
	status = "okay";

	phy0: ethernet-phy@4 {
	compatible = "ethernet-phy-ieee802.3-c22";
	reg = <4>;
	interrupts-extended = <&pinctrl RZG2L_GPIO(44, 2) IRQ_TYPE_LEVEL_LOW>;
	reset-gpios = <&pinctrl RZG2L_GPIO(44, 3) GPIO_ACTIVE_LOW>;
	};
	};

	&eth1 {
	pinctrl-0 = <&eth1_pins>;
	pinctrl-names = "default";
	phy-handle = <&phy1>;
	phy-mode = "rgmii-id";
	status = "okay";

	phy1: ethernet-phy@6 {
	compatible = "ethernet-phy-ieee802.3-c22";
	reg = <6>;
	interrupts-extended = <&pinctrl RZG2L_GPIO(43, 2) IRQ_TYPE_LEVEL_LOW>;
	reset-gpios = <&pinctrl RZG2L_GPIO(43, 3) GPIO_ACTIVE_LOW>;
	};
	};

	&extal_clk {
	clock-frequency = <24000000>;
	};

	&gpu {
	mali-supply = <&reg_1p1v>;
	};

	&i2c0 {
	pinctrl-0 = <&i2c0_pins>;
	pinctrl-names = "default";

	clock-frequency = <400000>;
	status = "okay";

	hdmi-bridge@48 {
	compatible = "lontium,lt8912b";
	reg = <0x48> ;
	reset-gpios = <&pinctrl RZG2L_GPIO(42, 2) GPIO_ACTIVE_LOW>;

	ports {
	#address-cells = <1>;
	#size-cells = <0>;

	port@0 {
	reg = <0>;

	lt8912_in: endpoint {
	data-lanes = <1 2 3 4>;
	remote-endpoint = <&dsi_out>;
	};
	};

	port@1 {
	reg = <1>;

	lt8912_out: endpoint {
	remote-endpoint = <&hdmi_con>;
	};
	};
	};
	};
	};

	&i2c1 {
	pinctrl-0 = <&i2c1_pins>;
	pinctrl-names = "default";
	clock-frequency = <100000>;
	status = "okay";
	};

	&i2c2 {
	pinctrl-0 = <&i2c2_pins>;
	pinctrl-names = "default";
	clock-frequency = <100000>;
	status = "okay";
	};

	&i2c3 {
	pinctrl-0 = <&i2c3_pins>;
	pinctrl-names = "default";
	clock-frequency = <100000>;
	status = "okay";
	};

	&mtu3 {
	status = "okay";
	};

	&ohci1 {
	status = "okay";
	};

	&ostm1 {
	status = "okay";
	};

	&ostm2 {
	status = "okay";
	};

	&phyrst {
	status = "okay";
	};

	&pinctrl {
	eth0_pins: eth0 {
	pinmux = <RZG2L_PORT_PINMUX(27, 1, 1)>, /* ET0_MDC */
	<RZG2L_PORT_PINMUX(28, 0, 1)>, /* ET0_MDIO */
	<RZG2L_PORT_PINMUX(20, 0, 1)>, /* ET0_TXC */
	<RZG2L_PORT_PINMUX(20, 1, 1)>, /* ET0_TX_CTL */
	<RZG2L_PORT_PINMUX(20, 2, 1)>, /* ET0_TXD0 */
	<RZG2L_PORT_PINMUX(21, 0, 1)>, /* ET0_TXD1 */
	<RZG2L_PORT_PINMUX(21, 1, 1)>, /* ET0_TXD2 */
	<RZG2L_PORT_PINMUX(22, 0, 1)>, /* ET0_TXD3 */
	<RZG2L_PORT_PINMUX(24, 0, 1)>, /* ET0_RXC */
	<RZG2L_PORT_PINMUX(24, 1, 1)>, /* ET0_RX_CTL */
	<RZG2L_PORT_PINMUX(25, 0, 1)>, /* ET0_RXD0 */
	<RZG2L_PORT_PINMUX(25, 1, 1)>, /* ET0_RXD1 */
	<RZG2L_PORT_PINMUX(26, 0, 1)>, /* ET0_RXD2 */
	<RZG2L_PORT_PINMUX(26, 1, 1)>; /* ET0_RXD3 */
	};

	eth1_pins: eth1 {
	pinmux = <RZG2L_PORT_PINMUX(37, 0, 1)>, /* ET1_MDC */
	<RZG2L_PORT_PINMUX(37, 1, 1)>, /* ET1_MDIO */
	<RZG2L_PORT_PINMUX(29, 0, 1)>, /* ET1_TXC */
	<RZG2L_PORT_PINMUX(29, 1, 1)>, /* ET1_TX_CTL */
	<RZG2L_PORT_PINMUX(30, 0, 1)>, /* ET1_TXD0 */
	<RZG2L_PORT_PINMUX(30, 1, 1)>, /* ET1_TXD1 */
	<RZG2L_PORT_PINMUX(31, 0, 1)>, /* ET1_TXD2 */
	<RZG2L_PORT_PINMUX(31, 1, 1)>, /* ET1_TXD3 */
	<RZG2L_PORT_PINMUX(33, 1, 1)>, /* ET1_RXC */
	<RZG2L_PORT_PINMUX(34, 0, 1)>, /* ET1_RX_CTL */
	<RZG2L_PORT_PINMUX(34, 1, 1)>, /* ET1_RXD0 */
	<RZG2L_PORT_PINMUX(35, 0, 1)>, /* ET1_RXD1 */
	<RZG2L_PORT_PINMUX(35, 1, 1)>, /* ET1_RXD2 */
	<RZG2L_PORT_PINMUX(36, 0, 1)>; /* ET1_RXD3 */
	};

	i2c0_pins: i2c0 {
	pins = "RIIC0_SDA", "RIIC0_SCL";
	input-enable;
	};

	i2c1_pins: i2c1 {
	pins = "RIIC1_SDA", "RIIC1_SCL";
	input-enable;
	};

	i2c2_pins: i2c2 {
	pinmux = <RZG2L_PORT_PINMUX(3, 0, 2)>, /* SDA */
	<RZG2L_PORT_PINMUX(3, 1, 2)>; /* SCL */
	};

	i2c3_pins: i2c3 {
	pinmux = <RZG2L_PORT_PINMUX(18, 0, 3)>, /* SDA */
	<RZG2L_PORT_PINMUX(18, 1, 3)>; /* SCL */
	};

	scif0_pins: scif0 {
	pinmux = <RZG2L_PORT_PINMUX(38, 0, 1)>, /* TxD */
	<RZG2L_PORT_PINMUX(38, 1, 1)>; /* RxD */
	};

	scif4_pins: scif4 {
	pinmux = <RZG2L_PORT_PINMUX(2, 0, 5)>, /* TxD */
	<RZG2L_PORT_PINMUX(2, 1, 5)>; /* RxD */
	};

	sdhi0_pins: sd0 {
	sd0-ctrl {
	pins = "SD0_CLK", "SD0_CMD";
	power-source = <1800>;
	};

	sd0-data {
	pins = "SD0_DATA0", "SD0_DATA1", "SD0_DATA2", "SD0_DATA3",
	"SD0_DATA4", "SD0_DATA5", "SD0_DATA6", "SD0_DATA7";
	power-source = <1800>;
	};

	sd0-rst {
	pins = "SD0_RST#";
	power-source = <1800>;
	};
	};
	};

	&scif0 {
	pinctrl-0 = <&scif0_pins>;
	pinctrl-names = "default";
	status = "okay";
	};

	&scif4 {
	pinctrl-0 = <&scif4_pins>;
	pinctrl-names = "default";
	status = "okay";
	};

	&sdhi0 {
	pinctrl-0 = <&sdhi0_pins>;
	pinctrl-1 = <&sdhi0_pins>;
	pinctrl-names = "default", "state_uhs";

	vmmc-supply = <&reg_3p3v>;
	vqmmc-supply = <&reg_1p8v>;
	bus-width = <8>;
	mmc-hs200-1_8v;
	non-removable;
	fixed-emmc-driver-type = <1>;
	status = "okay";
	};

	&usb2_phy1 {
	status = "okay";
	};