| Iterations: 100 | |
| Instructions: 1000 | |
| Total Cycles: 404 | |
| Total uOps: 1000 | |
| Dispatch Width: 4 | |
| uOps Per Cycle: 2.48 | |
| IPC: 2.48 | |
| Block RThroughput: 4.0 | |
| Instruction Info: | |
| [1]: #uOps | |
| [2]: Latency | |
| [3]: RThroughput | |
| [4]: MayLoad | |
| [5]: MayStore | |
| [6]: HasSideEffects (U) | |
| [1] [2] [3] [4] [5] [6] Instructions: | |
| 1 1 0.33 mov rax, rdi | |
| 1 1 0.33 cmp rcx, rdx | |
| 1 1 1.00 jbe .LBB5_2 | |
| 1 0 0.25 xor esi, esi | |
| 1 1 1.00 * mov qword ptr [rax], rsi | |
| 1 1 1.00 U ret | |
| 1 1 1.00 * mov qword ptr [rax + 8], rdx | |
| 1 1 1.00 * mov qword ptr [rax + 16], rcx | |
| 1 1 1.00 * mov qword ptr [rax], rsi | |
| 1 1 1.00 U ret | |
| Resources: | |
| [0] - SBDivider | |
| [1] - SBFPDivider | |
| [2] - SBPort0 | |
| [3] - SBPort1 | |
| [4] - SBPort4 | |
| [5] - SBPort5 | |
| [6.0] - SBPort23 | |
| [6.1] - SBPort23 | |
| Resource pressure per iteration: | |
| [0] [1] [2] [3] [4] [5] [6.0] [6.1] | |
| - - 0.99 1.00 4.00 3.01 2.00 2.00 | |
| Resource pressure by instruction: | |
| [0] [1] [2] [3] [4] [5] [6.0] [6.1] Instructions: | |
| - - 0.99 - - 0.01 - - mov rax, rdi | |
| - - - 1.00 - - - - cmp rcx, rdx | |
| - - - - - 1.00 - - jbe .LBB5_2 | |
| - - - - - - - - xor esi, esi | |
| - - - - 1.00 - - 1.00 mov qword ptr [rax], rsi | |
| - - - - - 1.00 - - ret | |
| - - - - 1.00 - 1.00 - mov qword ptr [rax + 8], rdx | |
| - - - - 1.00 - - 1.00 mov qword ptr [rax + 16], rcx | |
| - - - - 1.00 - 1.00 - mov qword ptr [rax], rsi | |
| - - - - - 1.00 - - ret |