| From 054b9f3ff63ba832d8aa6593c4734ab18c645252 Mon Sep 17 00:00:00 2001 |
| From: David Wang <davidwang@quantatw.com> |
| Date: Mon, 6 Nov 2023 14:36:35 +0800 |
| Subject: [PATCH 14/16] drivers: i2c: sync npcm i2c |
| |
| --- |
| drivers/i2c/busses/Kconfig | 8 +-- |
| drivers/i2c/busses/Makefile | 2 +- |
| drivers/i2c/busses/i2c-npcm7xx.c | 88 ++++++++++++++++---------------- |
| 3 files changed, 49 insertions(+), 49 deletions(-) |
| |
| diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig |
| index fea403431f22..a42f4079e119 100644 |
| --- a/drivers/i2c/busses/Kconfig |
| +++ b/drivers/i2c/busses/Kconfig |
| @@ -814,13 +814,13 @@ config I2C_NOMADIK |
| I2C interface from ST-Ericsson's Nomadik and Ux500 architectures, |
| as well as the STA2X11 PCIe I/O HUB. |
| |
| -config I2C_NPCM7XX |
| +config I2C_NPCM |
| tristate "Nuvoton I2C Controller" |
| - depends on ARCH_NPCM7XX || COMPILE_TEST |
| + depends on ARCH_NPCM || COMPILE_TEST |
| help |
| If you say yes to this option, support will be included for the |
| - Nuvoton I2C controller, which is available on the NPCM7xx BMC |
| - controller. |
| + Nuvoton I2C controller, which is available on the NPCM BMC |
| + controllers. |
| Driver can also support slave mode (select I2C_SLAVE). |
| |
| config I2C_OCORES |
| diff --git a/drivers/i2c/busses/Makefile b/drivers/i2c/busses/Makefile |
| index 1336b04f40e2..90943bb84f4e 100644 |
| --- a/drivers/i2c/busses/Makefile |
| +++ b/drivers/i2c/busses/Makefile |
| @@ -80,7 +80,7 @@ obj-$(CONFIG_I2C_MT7621) += i2c-mt7621.o |
| obj-$(CONFIG_I2C_MV64XXX) += i2c-mv64xxx.o |
| obj-$(CONFIG_I2C_MXS) += i2c-mxs.o |
| obj-$(CONFIG_I2C_NOMADIK) += i2c-nomadik.o |
| -obj-$(CONFIG_I2C_NPCM7XX) += i2c-npcm7xx.o |
| +obj-$(CONFIG_I2C_NPCM) += i2c-npcm7xx.o |
| obj-$(CONFIG_I2C_OCORES) += i2c-ocores.o |
| obj-$(CONFIG_I2C_OMAP) += i2c-omap.o |
| obj-$(CONFIG_I2C_OWL) += i2c-owl.o |
| diff --git a/drivers/i2c/busses/i2c-npcm7xx.c b/drivers/i2c/busses/i2c-npcm7xx.c |
| index 7e71b89bb1fd..3ba701dbbbaa 100644 |
| --- a/drivers/i2c/busses/i2c-npcm7xx.c |
| +++ b/drivers/i2c/busses/i2c-npcm7xx.c |
| @@ -1,5 +1,4 @@ |
| // SPDX-License-Identifier: GPL-2.0 |
| -// nuvoton/NPCM-6.1-OpenBMC: 13848588581d605fe538ee250009b5076164fb7d |
| /* |
| * Nuvoton NPCM7xx I2C Controller driver |
| * |
| @@ -107,7 +106,7 @@ enum i2c_addr { |
| #define NPCM_I2CCST3 0x19 |
| #define I2C_VER 0x1F |
| |
| -/* BANK 0 regs */ |
| +/*BANK0 regs*/ |
| #define NPCM_I2CADDR3 0x10 |
| #define NPCM_I2CADDR7 0x11 |
| #define NPCM_I2CADDR4 0x12 |
| @@ -116,20 +115,6 @@ enum i2c_addr { |
| #define NPCM_I2CADDR9 0x15 |
| #define NPCM_I2CADDR6 0x16 |
| #define NPCM_I2CADDR10 0x17 |
| -#define NPCM_I2CCTL4 0x1A |
| -#define NPCM_I2CCTL5 0x1B |
| -#define NPCM_I2CSCLLT 0x1C /* SCL Low Time */ |
| -#define NPCM_I2CFIF_CTL 0x1D /* FIFO Control */ |
| -#define NPCM_I2CSCLHT 0x1E /* SCL High Time */ |
| - |
| -/* BANK 1 regs */ |
| -#define NPCM_I2CFIF_CTS 0x10 /* Both FIFOs Control and Status */ |
| -#define NPCM_I2CTXF_CTL 0x12 /* Tx-FIFO Control */ |
| -#define NPCM_I2CT_OUT 0x14 /* Bus T.O. */ |
| -#define NPCM_I2CPEC 0x16 /* PEC Data */ |
| -#define NPCM_I2CTXF_STS 0x1A /* Tx-FIFO Status */ |
| -#define NPCM_I2CRXF_STS 0x1C /* Rx-FIFO Status */ |
| -#define NPCM_I2CRXF_CTL 0x1E /* Rx-FIFO Control */ |
| |
| #if IS_ENABLED(CONFIG_I2C_SLAVE) |
| /* |
| @@ -146,51 +131,66 @@ static const int npcm_i2caddr[I2C_NUM_OWN_ADDR] = { |
| }; |
| #endif |
| |
| +#define NPCM_I2CCTL4 0x1A |
| +#define NPCM_I2CCTL5 0x1B |
| +#define NPCM_I2CSCLLT 0x1C /* SCL Low Time */ |
| +#define NPCM_I2CFIF_CTL 0x1D /* FIFO Control */ |
| +#define NPCM_I2CSCLHT 0x1E /* SCL High Time */ |
| + |
| +/* BANK 1 regs */ |
| +#define NPCM_I2CFIF_CTS 0x10 /* Both FIFOs Control and Status */ |
| +#define NPCM_I2CTXF_CTL 0x12 /* Tx-FIFO Control */ |
| +#define NPCM_I2CT_OUT 0x14 /* Bus T.O. */ |
| +#define NPCM_I2CPEC 0x16 /* PEC Data */ |
| +#define NPCM_I2CTXF_STS 0x1A /* Tx-FIFO Status */ |
| +#define NPCM_I2CRXF_STS 0x1C /* Rx-FIFO Status */ |
| +#define NPCM_I2CRXF_CTL 0x1E /* Rx-FIFO Control */ |
| + |
| /* NPCM_I2CST reg fields */ |
| -#define NPCM_I2CST_XMIT BIT(0) /* Transmit mode */ |
| -#define NPCM_I2CST_MASTER BIT(1) /* Master mode */ |
| -#define NPCM_I2CST_NMATCH BIT(2) /* New match */ |
| -#define NPCM_I2CST_STASTR BIT(3) /* Stall after start */ |
| -#define NPCM_I2CST_NEGACK BIT(4) /* Negative ACK */ |
| -#define NPCM_I2CST_BER BIT(5) /* Bus error */ |
| -#define NPCM_I2CST_SDAST BIT(6) /* SDA status */ |
| -#define NPCM_I2CST_SLVSTP BIT(7) /* Slave stop */ |
| +#define NPCM_I2CST_XMIT BIT(0) |
| +#define NPCM_I2CST_MASTER BIT(1) |
| +#define NPCM_I2CST_NMATCH BIT(2) |
| +#define NPCM_I2CST_STASTR BIT(3) |
| +#define NPCM_I2CST_NEGACK BIT(4) |
| +#define NPCM_I2CST_BER BIT(5) |
| +#define NPCM_I2CST_SDAST BIT(6) |
| +#define NPCM_I2CST_SLVSTP BIT(7) |
| |
| /* NPCM_I2CCST reg fields */ |
| -#define NPCM_I2CCST_BUSY BIT(0) /* Busy */ |
| -#define NPCM_I2CCST_BB BIT(1) /* Bus busy */ |
| -#define NPCM_I2CCST_MATCH BIT(2) /* Address match */ |
| -#define NPCM_I2CCST_GCMATCH BIT(3) /* Global call match */ |
| -#define NPCM_I2CCST_TSDA BIT(4) /* Test SDA line */ |
| -#define NPCM_I2CCST_TGSCL BIT(5) /* Toggle SCL line */ |
| -#define NPCM_I2CCST_MATCHAF BIT(6) /* Match address field */ |
| -#define NPCM_I2CCST_ARPMATCH BIT(7) /* ARP address match */ |
| +#define NPCM_I2CCST_BUSY BIT(0) |
| +#define NPCM_I2CCST_BB BIT(1) |
| +#define NPCM_I2CCST_MATCH BIT(2) |
| +#define NPCM_I2CCST_GCMATCH BIT(3) |
| +#define NPCM_I2CCST_TSDA BIT(4) |
| +#define NPCM_I2CCST_TGSCL BIT(5) |
| +#define NPCM_I2CCST_MATCHAF BIT(6) |
| +#define NPCM_I2CCST_ARPMATCH BIT(7) |
| |
| /* NPCM_I2CCTL1 reg fields */ |
| -#define NPCM_I2CCTL1_START BIT(0) /* Generate start condition */ |
| -#define NPCM_I2CCTL1_STOP BIT(1) /* Generate stop condition */ |
| -#define NPCM_I2CCTL1_INTEN BIT(2) /* Interrupt enable */ |
| +#define NPCM_I2CCTL1_START BIT(0) |
| +#define NPCM_I2CCTL1_STOP BIT(1) |
| +#define NPCM_I2CCTL1_INTEN BIT(2) |
| #define NPCM_I2CCTL1_EOBINTE BIT(3) |
| #define NPCM_I2CCTL1_ACK BIT(4) |
| -#define NPCM_I2CCTL1_GCMEN BIT(5) /* Global call match enable */ |
| -#define NPCM_I2CCTL1_NMINTE BIT(6) /* New match interrupt enable */ |
| -#define NPCM_I2CCTL1_STASTRE BIT(7) /* Stall after start enable */ |
| +#define NPCM_I2CCTL1_GCMEN BIT(5) |
| +#define NPCM_I2CCTL1_NMINTE BIT(6) |
| +#define NPCM_I2CCTL1_STASTRE BIT(7) |
| |
| /* RW1S fields (inside a RW reg): */ |
| #define NPCM_I2CCTL1_RWS \ |
| (NPCM_I2CCTL1_START | NPCM_I2CCTL1_STOP | NPCM_I2CCTL1_ACK) |
| |
| /* npcm_i2caddr reg fields */ |
| -#define NPCM_I2CADDR_A GENMASK(6, 0) /* Address */ |
| -#define NPCM_I2CADDR_SAEN BIT(7) /* Slave address enable */ |
| +#define NPCM_I2CADDR_A GENMASK(6, 0) |
| +#define NPCM_I2CADDR_SAEN BIT(7) |
| |
| /* NPCM_I2CCTL2 reg fields */ |
| -#define I2CCTL2_ENABLE BIT(0) /* Module enable */ |
| -#define I2CCTL2_SCLFRQ6_0 GENMASK(7, 1) /* Bits 0:6 of frequency divisor */ |
| +#define I2CCTL2_ENABLE BIT(0) |
| +#define I2CCTL2_SCLFRQ6_0 GENMASK(7, 1) |
| |
| /* NPCM_I2CCTL3 reg fields */ |
| -#define I2CCTL3_SCLFRQ8_7 GENMASK(1, 0) /* Bits 7:8 of frequency divisor */ |
| -#define I2CCTL3_ARPMEN BIT(2) /* ARP match enable */ |
| +#define I2CCTL3_SCLFRQ8_7 GENMASK(1, 0) |
| +#define I2CCTL3_ARPMEN BIT(2) |
| #define I2CCTL3_IDL_START BIT(3) |
| #define I2CCTL3_400K_MODE BIT(4) |
| #define I2CCTL3_BNK_SEL BIT(5) |
| -- |
| 2.25.1 |
| |
