gbmcweb master: SRCREV bump dc357ba8f1..3c072ee195

gBMC Team (3):
      Support uint64_t Bus and Address properties for RawEeproms.
      Integrate BIOS configuration updates into memory capacity registry operations.
      Disable cached PWM writes in tlBMC Thermal Control

Fusion-Link: fusion2 N/A
Tested: fusion2.corp.google.com/a713be96-5be8-309b-812f-fe0f138fec25
Google-Bug-Id: 541287798
Google-Bug-Id: 545704112
Google-Bug-Id: 558424309
Change-Id: I67d837b142392cace776fe859d7019da208e1b19
Signed-off-by: James Zheng <alphetis@google.com>

recipes-phosphor/interfaces/gbmcweb.inc

diff --git a/recipes-phosphor/interfaces/gbmcweb.inc b/recipes-phosphor/interfaces/gbmcweb.inc
index a2a4c29..9f2266e 100644
--- a/recipes-phosphor/interfaces/gbmcweb.inc
+++ b/recipes-phosphor/interfaces/gbmcweb.inc
@@ -1,2 +1,2 @@
 GBMCWEB_SRC_URI = "git://gbmc.googlesource.com/gbmcweb;branch=master;protocol=https"
-GBMCWEB_SRCREV = "dc357ba8f1bfb289fbaded2052b7f43391dd2747"
+GBMCWEB_SRCREV = "3c072ee195ecfb4041938479331b98c58043f76e"