blob: f51fd1e6234e91bf6bb4153d7558448f3e388304 [file] [log] [blame]
From a75a1ed032e1bf2adc6691ab8d9e043281a6126e Mon Sep 17 00:00:00 2001
From: Tom Tung <tomtung@google.com>
Date: Tue, 8 Feb 2022 16:57:04 +0800
Subject: [PATCH 2/2] kernel: Ensure only 3 byte read command can be sent
Patch Tracking Bug: b/232026313
Upstream info / review: N/A
Upstream-Status: Inappropriate [configuration]
Justification: This patch probably cannot be upstreamed since it
makes BMC use 3-byte read command with 4-byte address.
Aspeed-g6 needs this because Hoth doesn't support 4-byte read
command and our flash chip supports 3-byte read command with
4-byte addresses.
Signed-off-by: Tom Tung <tomtung@google.com>
---
drivers/spi/spi-aspeed-smc.c | 11 +++++++----
1 file changed, 7 insertions(+), 4 deletions(-)
diff --git a/drivers/spi/spi-aspeed-smc.c b/drivers/spi/spi-aspeed-smc.c
index 496f3e1e9079..925578192a78 100644
--- a/drivers/spi/spi-aspeed-smc.c
+++ b/drivers/spi/spi-aspeed-smc.c
@@ -319,7 +319,7 @@ static int do_aspeed_spi_exec_op(struct spi_mem *mem, const struct spi_mem_op *o
/* 4BYTE address mode */
if (op->addr.nbytes) {
if (op->addr.nbytes == 4)
- addr_mode |= (0x11 << chip->cs);
+ addr_mode |= (0x01 << chip->cs);
else
addr_mode &= ~(0x11 << chip->cs);
@@ -581,9 +581,12 @@ static int aspeed_spi_dirmap_create(struct spi_mem_dirmap_desc *desc)
if (op->addr.nbytes) {
u32 addr_mode = readl(aspi->regs + CE_CTRL_REG);
- if (op->addr.nbytes == 4)
- addr_mode |= (0x11 << chip->cs);
- else
+ if (op->addr.nbytes == 4) {
+ // Ensure the 4th bit of FMC04 is set to zero so that
+ // 3 byte read command will be sent.
+ addr_mode &= ~0x10;
+ addr_mode |= (0x01 << chip->cs);
+ } else
addr_mode &= ~(0x11 << chip->cs);
writel(addr_mode, aspi->regs + CE_CTRL_REG);
--
2.36.0.512.ge40c2bad7a-goog