| // SPDX-License-Identifier: GPL-2.0 | |
| #include <dt-bindings/clock/tegra20-car.h> | |
| #include <dt-bindings/gpio/tegra-gpio.h> | |
| #include <dt-bindings/memory/tegra20-mc.h> | |
| #include <dt-bindings/pinctrl/pinctrl-tegra.h> | |
| #include <dt-bindings/interrupt-controller/arm-gic.h> | |
| #include <dt-bindings/soc/tegra-pmc.h> | |
| #include "tegra20-peripherals-opp.dtsi" | |
| / { | |
| compatible = "nvidia,tegra20"; | |
| interrupt-parent = <&lic>; | |
| #address-cells = <1>; | |
| #size-cells = <1>; | |
| memory@0 { | |
| device_type = "memory"; | |
| reg = <0 0>; | |
| }; | |
| sram@40000000 { | |
| compatible = "mmio-sram"; | |
| reg = <0x40000000 0x40000>; | |
| #address-cells = <1>; | |
| #size-cells = <1>; | |
| ranges = <0 0x40000000 0x40000>; | |
| vde_pool: sram@400 { | |
| reg = <0x400 0x3fc00>; | |
| pool; | |
| }; | |
| }; | |
| host1x@50000000 { | |
| compatible = "nvidia,tegra20-host1x"; | |
| reg = <0x50000000 0x00024000>; | |
| interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */ | |
| <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */ | |
| interrupt-names = "syncpt", "host1x"; | |
| clocks = <&tegra_car TEGRA20_CLK_HOST1X>; | |
| clock-names = "host1x"; | |
| resets = <&tegra_car 28>, <&mc TEGRA20_MC_RESET_HC>; | |
| reset-names = "host1x", "mc"; | |
| power-domains = <&pd_core>; | |
| operating-points-v2 = <&host1x_dvfs_opp_table>; | |
| #address-cells = <1>; | |
| #size-cells = <1>; | |
| ranges = <0x54000000 0x54000000 0x04000000>; | |
| mpe@54040000 { | |
| compatible = "nvidia,tegra20-mpe"; | |
| reg = <0x54040000 0x00040000>; | |
| interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; | |
| clocks = <&tegra_car TEGRA20_CLK_MPE>; | |
| resets = <&tegra_car 60>; | |
| reset-names = "mpe"; | |
| power-domains = <&pd_mpe>; | |
| operating-points-v2 = <&mpe_dvfs_opp_table>; | |
| status = "disabled"; | |
| }; | |
| vi@54080000 { | |
| compatible = "nvidia,tegra20-vi"; | |
| reg = <0x54080000 0x00040000>; | |
| interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; | |
| clocks = <&tegra_car TEGRA20_CLK_VI>; | |
| resets = <&tegra_car 20>; | |
| reset-names = "vi"; | |
| power-domains = <&pd_venc>; | |
| operating-points-v2 = <&vi_dvfs_opp_table>; | |
| status = "disabled"; | |
| }; | |
| epp@540c0000 { | |
| compatible = "nvidia,tegra20-epp"; | |
| reg = <0x540c0000 0x00040000>; | |
| interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; | |
| clocks = <&tegra_car TEGRA20_CLK_EPP>; | |
| resets = <&tegra_car 19>; | |
| reset-names = "epp"; | |
| power-domains = <&pd_core>; | |
| operating-points-v2 = <&epp_dvfs_opp_table>; | |
| status = "disabled"; | |
| }; | |
| isp@54100000 { | |
| compatible = "nvidia,tegra20-isp"; | |
| reg = <0x54100000 0x00040000>; | |
| interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; | |
| clocks = <&tegra_car TEGRA20_CLK_ISP>; | |
| resets = <&tegra_car 23>; | |
| reset-names = "isp"; | |
| power-domains = <&pd_venc>; | |
| status = "disabled"; | |
| }; | |
| gr2d@54140000 { | |
| compatible = "nvidia,tegra20-gr2d"; | |
| reg = <0x54140000 0x00040000>; | |
| interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; | |
| clocks = <&tegra_car TEGRA20_CLK_GR2D>; | |
| resets = <&tegra_car 21>, <&mc TEGRA20_MC_RESET_2D>; | |
| reset-names = "2d", "mc"; | |
| power-domains = <&pd_core>; | |
| operating-points-v2 = <&gr2d_dvfs_opp_table>; | |
| }; | |
| gr3d@54180000 { | |
| compatible = "nvidia,tegra20-gr3d"; | |
| reg = <0x54180000 0x00040000>; | |
| clocks = <&tegra_car TEGRA20_CLK_GR3D>; | |
| resets = <&tegra_car 24>, <&mc TEGRA20_MC_RESET_3D>; | |
| reset-names = "3d", "mc"; | |
| power-domains = <&pd_3d>; | |
| operating-points-v2 = <&gr3d_dvfs_opp_table>; | |
| }; | |
| dc@54200000 { | |
| compatible = "nvidia,tegra20-dc"; | |
| reg = <0x54200000 0x00040000>; | |
| interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; | |
| clocks = <&tegra_car TEGRA20_CLK_DISP1>, | |
| <&tegra_car TEGRA20_CLK_PLL_P>; | |
| clock-names = "dc", "parent"; | |
| resets = <&tegra_car 27>; | |
| reset-names = "dc"; | |
| power-domains = <&pd_core>; | |
| operating-points-v2 = <&disp1_dvfs_opp_table>; | |
| nvidia,head = <0>; | |
| interconnects = <&mc TEGRA20_MC_DISPLAY0A &emc>, | |
| <&mc TEGRA20_MC_DISPLAY0B &emc>, | |
| <&mc TEGRA20_MC_DISPLAY1B &emc>, | |
| <&mc TEGRA20_MC_DISPLAY0C &emc>, | |
| <&mc TEGRA20_MC_DISPLAYHC &emc>; | |
| interconnect-names = "wina", | |
| "winb", | |
| "winb-vfilter", | |
| "winc", | |
| "cursor"; | |
| rgb { | |
| status = "disabled"; | |
| }; | |
| }; | |
| dc@54240000 { | |
| compatible = "nvidia,tegra20-dc"; | |
| reg = <0x54240000 0x00040000>; | |
| interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; | |
| clocks = <&tegra_car TEGRA20_CLK_DISP2>, | |
| <&tegra_car TEGRA20_CLK_PLL_P>; | |
| clock-names = "dc", "parent"; | |
| resets = <&tegra_car 26>; | |
| reset-names = "dc"; | |
| power-domains = <&pd_core>; | |
| operating-points-v2 = <&disp2_dvfs_opp_table>; | |
| nvidia,head = <1>; | |
| interconnects = <&mc TEGRA20_MC_DISPLAY0AB &emc>, | |
| <&mc TEGRA20_MC_DISPLAY0BB &emc>, | |
| <&mc TEGRA20_MC_DISPLAY1BB &emc>, | |
| <&mc TEGRA20_MC_DISPLAY0CB &emc>, | |
| <&mc TEGRA20_MC_DISPLAYHCB &emc>; | |
| interconnect-names = "wina", | |
| "winb", | |
| "winb-vfilter", | |
| "winc", | |
| "cursor"; | |
| rgb { | |
| status = "disabled"; | |
| }; | |
| }; | |
| tegra_hdmi: hdmi@54280000 { | |
| compatible = "nvidia,tegra20-hdmi"; | |
| reg = <0x54280000 0x00040000>; | |
| interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; | |
| clocks = <&tegra_car TEGRA20_CLK_HDMI>, | |
| <&tegra_car TEGRA20_CLK_PLL_D_OUT0>; | |
| clock-names = "hdmi", "parent"; | |
| resets = <&tegra_car 51>; | |
| reset-names = "hdmi"; | |
| power-domains = <&pd_core>; | |
| operating-points-v2 = <&hdmi_dvfs_opp_table>; | |
| #sound-dai-cells = <0>; | |
| status = "disabled"; | |
| }; | |
| tvo@542c0000 { | |
| compatible = "nvidia,tegra20-tvo"; | |
| reg = <0x542c0000 0x00040000>; | |
| interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; | |
| clocks = <&tegra_car TEGRA20_CLK_TVO>; | |
| power-domains = <&pd_core>; | |
| operating-points-v2 = <&tvo_dvfs_opp_table>; | |
| status = "disabled"; | |
| }; | |
| dsi@54300000 { | |
| compatible = "nvidia,tegra20-dsi"; | |
| reg = <0x54300000 0x00040000>; | |
| clocks = <&tegra_car TEGRA20_CLK_DSI>, | |
| <&tegra_car TEGRA20_CLK_PLL_D_OUT0>; | |
| clock-names = "dsi", "parent"; | |
| resets = <&tegra_car 48>; | |
| reset-names = "dsi"; | |
| power-domains = <&pd_core>; | |
| operating-points-v2 = <&dsi_dvfs_opp_table>; | |
| status = "disabled"; | |
| }; | |
| }; | |
| timer@50040600 { | |
| compatible = "arm,cortex-a9-twd-timer"; | |
| interrupt-parent = <&intc>; | |
| reg = <0x50040600 0x20>; | |
| interrupts = <GIC_PPI 13 | |
| (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>; | |
| clocks = <&tegra_car TEGRA20_CLK_TWD>; | |
| }; | |
| intc: interrupt-controller@50041000 { | |
| compatible = "arm,cortex-a9-gic"; | |
| reg = <0x50041000 0x1000>, | |
| <0x50040100 0x0100>; | |
| interrupt-controller; | |
| #interrupt-cells = <3>; | |
| interrupt-parent = <&intc>; | |
| }; | |
| cache-controller@50043000 { | |
| compatible = "arm,pl310-cache"; | |
| reg = <0x50043000 0x1000>; | |
| arm,data-latency = <5 5 2>; | |
| arm,tag-latency = <4 4 2>; | |
| cache-unified; | |
| cache-level = <2>; | |
| }; | |
| lic: interrupt-controller@60004000 { | |
| compatible = "nvidia,tegra20-ictlr"; | |
| reg = <0x60004000 0x100>, | |
| <0x60004100 0x50>, | |
| <0x60004200 0x50>, | |
| <0x60004300 0x50>; | |
| interrupt-controller; | |
| #interrupt-cells = <3>; | |
| interrupt-parent = <&intc>; | |
| }; | |
| timer@60005000 { | |
| compatible = "nvidia,tegra20-timer"; | |
| reg = <0x60005000 0x60>; | |
| interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, | |
| <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, | |
| <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, | |
| <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; | |
| clocks = <&tegra_car TEGRA20_CLK_TIMER>; | |
| }; | |
| tegra_car: clock@60006000 { | |
| compatible = "nvidia,tegra20-car"; | |
| reg = <0x60006000 0x1000>; | |
| #clock-cells = <1>; | |
| #reset-cells = <1>; | |
| sclk { | |
| compatible = "nvidia,tegra20-sclk"; | |
| clocks = <&tegra_car TEGRA20_CLK_SCLK>; | |
| power-domains = <&pd_core>; | |
| operating-points-v2 = <&sclk_dvfs_opp_table>; | |
| }; | |
| }; | |
| flow-controller@60007000 { | |
| compatible = "nvidia,tegra20-flowctrl"; | |
| reg = <0x60007000 0x1000>; | |
| }; | |
| apbdma: dma@6000a000 { | |
| compatible = "nvidia,tegra20-apbdma"; | |
| reg = <0x6000a000 0x1200>; | |
| interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, | |
| <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, | |
| <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, | |
| <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, | |
| <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, | |
| <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, | |
| <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, | |
| <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, | |
| <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, | |
| <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, | |
| <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, | |
| <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, | |
| <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, | |
| <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, | |
| <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, | |
| <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; | |
| clocks = <&tegra_car TEGRA20_CLK_APBDMA>; | |
| resets = <&tegra_car 34>; | |
| reset-names = "dma"; | |
| #dma-cells = <1>; | |
| }; | |
| ahb@6000c000 { | |
| compatible = "nvidia,tegra20-ahb"; | |
| reg = <0x6000c000 0x110>; /* AHB Arbitration + Gizmo Controller */ | |
| }; | |
| gpio: gpio@6000d000 { | |
| compatible = "nvidia,tegra20-gpio"; | |
| reg = <0x6000d000 0x1000>; | |
| interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, | |
| <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, | |
| <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, | |
| <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, | |
| <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, | |
| <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, | |
| <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; | |
| #gpio-cells = <2>; | |
| gpio-controller; | |
| #interrupt-cells = <2>; | |
| interrupt-controller; | |
| gpio-ranges = <&pinmux 0 0 224>; | |
| }; | |
| vde@6001a000 { | |
| compatible = "nvidia,tegra20-vde"; | |
| reg = <0x6001a000 0x1000>, /* Syntax Engine */ | |
| <0x6001b000 0x1000>, /* Video Bitstream Engine */ | |
| <0x6001c000 0x100>, /* Macroblock Engine */ | |
| <0x6001c200 0x100>, /* Post-processing Engine */ | |
| <0x6001c400 0x100>, /* Motion Compensation Engine */ | |
| <0x6001c600 0x100>, /* Transform Engine */ | |
| <0x6001c800 0x100>, /* Pixel prediction block */ | |
| <0x6001ca00 0x100>, /* Video DMA */ | |
| <0x6001d800 0x300>; /* Video frame controls */ | |
| reg-names = "sxe", "bsev", "mbe", "ppe", "mce", | |
| "tfe", "ppb", "vdma", "frameid"; | |
| iram = <&vde_pool>; /* IRAM region */ | |
| interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, /* Sync token interrupt */ | |
| <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, /* BSE-V interrupt */ | |
| <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; /* SXE interrupt */ | |
| interrupt-names = "sync-token", "bsev", "sxe"; | |
| clocks = <&tegra_car TEGRA20_CLK_VDE>; | |
| reset-names = "vde", "mc"; | |
| resets = <&tegra_car 61>, <&mc TEGRA20_MC_RESET_VDE>; | |
| power-domains = <&pd_vde>; | |
| operating-points-v2 = <&vde_dvfs_opp_table>; | |
| }; | |
| pinmux: pinmux@70000014 { | |
| compatible = "nvidia,tegra20-pinmux"; | |
| reg = <0x70000014 0x10>, /* Tri-state registers */ | |
| <0x70000080 0x20>, /* Mux registers */ | |
| <0x700000a0 0x14>, /* Pull-up/down registers */ | |
| <0x70000868 0xa8>; /* Pad control registers */ | |
| }; | |
| apbmisc@70000800 { | |
| compatible = "nvidia,tegra20-apbmisc"; | |
| reg = <0x70000800 0x64>, /* Chip revision */ | |
| <0x70000008 0x04>; /* Strapping options */ | |
| }; | |
| das@70000c00 { | |
| compatible = "nvidia,tegra20-das"; | |
| reg = <0x70000c00 0x80>; | |
| }; | |
| tegra_ac97: ac97@70002000 { | |
| compatible = "nvidia,tegra20-ac97"; | |
| reg = <0x70002000 0x200>; | |
| interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; | |
| clocks = <&tegra_car TEGRA20_CLK_AC97>; | |
| resets = <&tegra_car 3>; | |
| reset-names = "ac97"; | |
| dmas = <&apbdma 12>, <&apbdma 12>; | |
| dma-names = "rx", "tx"; | |
| status = "disabled"; | |
| }; | |
| tegra_spdif: spdif@70002400 { | |
| compatible = "nvidia,tegra20-spdif"; | |
| reg = <0x70002400 0x200>; | |
| interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; | |
| clocks = <&tegra_car TEGRA20_CLK_SPDIF_OUT>, | |
| <&tegra_car TEGRA20_CLK_SPDIF_IN>; | |
| clock-names = "out", "in"; | |
| resets = <&tegra_car 10>; | |
| dmas = <&apbdma 3>, <&apbdma 3>; | |
| dma-names = "rx", "tx"; | |
| #sound-dai-cells = <0>; | |
| status = "disabled"; | |
| assigned-clocks = <&tegra_car TEGRA20_CLK_SPDIF_OUT>; | |
| assigned-clock-parents = <&tegra_car TEGRA20_CLK_PLL_A_OUT0>; | |
| }; | |
| tegra_i2s1: i2s@70002800 { | |
| compatible = "nvidia,tegra20-i2s"; | |
| reg = <0x70002800 0x200>; | |
| interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; | |
| clocks = <&tegra_car TEGRA20_CLK_I2S1>; | |
| resets = <&tegra_car 11>; | |
| reset-names = "i2s"; | |
| dmas = <&apbdma 2>, <&apbdma 2>; | |
| dma-names = "rx", "tx"; | |
| status = "disabled"; | |
| }; | |
| tegra_i2s2: i2s@70002a00 { | |
| compatible = "nvidia,tegra20-i2s"; | |
| reg = <0x70002a00 0x200>; | |
| interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; | |
| clocks = <&tegra_car TEGRA20_CLK_I2S2>; | |
| resets = <&tegra_car 18>; | |
| reset-names = "i2s"; | |
| dmas = <&apbdma 1>, <&apbdma 1>; | |
| dma-names = "rx", "tx"; | |
| status = "disabled"; | |
| }; | |
| /* | |
| * There are two serial driver i.e. 8250 based simple serial | |
| * driver and APB DMA based serial driver for higher baudrate | |
| * and performace. To enable the 8250 based driver, the compatible | |
| * is "nvidia,tegra20-uart" and to enable the APB DMA based serial | |
| * driver, the compatible is "nvidia,tegra20-hsuart". | |
| */ | |
| uarta: serial@70006000 { | |
| compatible = "nvidia,tegra20-uart"; | |
| reg = <0x70006000 0x40>; | |
| reg-shift = <2>; | |
| interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; | |
| clocks = <&tegra_car TEGRA20_CLK_UARTA>; | |
| resets = <&tegra_car 6>; | |
| dmas = <&apbdma 8>, <&apbdma 8>; | |
| dma-names = "rx", "tx"; | |
| status = "disabled"; | |
| }; | |
| uartb: serial@70006040 { | |
| compatible = "nvidia,tegra20-uart"; | |
| reg = <0x70006040 0x40>; | |
| reg-shift = <2>; | |
| interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; | |
| clocks = <&tegra_car TEGRA20_CLK_UARTB>; | |
| resets = <&tegra_car 7>; | |
| dmas = <&apbdma 9>, <&apbdma 9>; | |
| dma-names = "rx", "tx"; | |
| status = "disabled"; | |
| }; | |
| uartc: serial@70006200 { | |
| compatible = "nvidia,tegra20-uart"; | |
| reg = <0x70006200 0x100>; | |
| reg-shift = <2>; | |
| interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; | |
| clocks = <&tegra_car TEGRA20_CLK_UARTC>; | |
| resets = <&tegra_car 55>; | |
| dmas = <&apbdma 10>, <&apbdma 10>; | |
| dma-names = "rx", "tx"; | |
| status = "disabled"; | |
| }; | |
| uartd: serial@70006300 { | |
| compatible = "nvidia,tegra20-uart"; | |
| reg = <0x70006300 0x100>; | |
| reg-shift = <2>; | |
| interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; | |
| clocks = <&tegra_car TEGRA20_CLK_UARTD>; | |
| resets = <&tegra_car 65>; | |
| dmas = <&apbdma 19>, <&apbdma 19>; | |
| dma-names = "rx", "tx"; | |
| status = "disabled"; | |
| }; | |
| uarte: serial@70006400 { | |
| compatible = "nvidia,tegra20-uart"; | |
| reg = <0x70006400 0x100>; | |
| reg-shift = <2>; | |
| interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; | |
| clocks = <&tegra_car TEGRA20_CLK_UARTE>; | |
| resets = <&tegra_car 66>; | |
| dmas = <&apbdma 20>, <&apbdma 20>; | |
| dma-names = "rx", "tx"; | |
| status = "disabled"; | |
| }; | |
| nand-controller@70008000 { | |
| compatible = "nvidia,tegra20-nand"; | |
| reg = <0x70008000 0x100>; | |
| #address-cells = <1>; | |
| #size-cells = <0>; | |
| interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; | |
| clocks = <&tegra_car TEGRA20_CLK_NDFLASH>; | |
| clock-names = "nand"; | |
| resets = <&tegra_car 13>; | |
| reset-names = "nand"; | |
| assigned-clocks = <&tegra_car TEGRA20_CLK_NDFLASH>; | |
| assigned-clock-rates = <150000000>; | |
| power-domains = <&pd_core>; | |
| operating-points-v2 = <&ndflash_dvfs_opp_table>; | |
| status = "disabled"; | |
| }; | |
| gmi@70009000 { | |
| compatible = "nvidia,tegra20-gmi"; | |
| reg = <0x70009000 0x1000>; | |
| #address-cells = <2>; | |
| #size-cells = <1>; | |
| ranges = <0 0 0xd0000000 0xfffffff>; | |
| clocks = <&tegra_car TEGRA20_CLK_NOR>; | |
| clock-names = "gmi"; | |
| resets = <&tegra_car 42>; | |
| reset-names = "gmi"; | |
| power-domains = <&pd_core>; | |
| operating-points-v2 = <&nor_dvfs_opp_table>; | |
| status = "disabled"; | |
| }; | |
| pwm: pwm@7000a000 { | |
| compatible = "nvidia,tegra20-pwm"; | |
| reg = <0x7000a000 0x100>; | |
| #pwm-cells = <2>; | |
| clocks = <&tegra_car TEGRA20_CLK_PWM>; | |
| resets = <&tegra_car 17>; | |
| reset-names = "pwm"; | |
| status = "disabled"; | |
| }; | |
| i2c@7000c000 { | |
| compatible = "nvidia,tegra20-i2c"; | |
| reg = <0x7000c000 0x100>; | |
| interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; | |
| #address-cells = <1>; | |
| #size-cells = <0>; | |
| clocks = <&tegra_car TEGRA20_CLK_I2C1>, | |
| <&tegra_car TEGRA20_CLK_PLL_P_OUT3>; | |
| clock-names = "div-clk", "fast-clk"; | |
| resets = <&tegra_car 12>; | |
| reset-names = "i2c"; | |
| dmas = <&apbdma 21>, <&apbdma 21>; | |
| dma-names = "rx", "tx"; | |
| status = "disabled"; | |
| }; | |
| spi@7000c380 { | |
| compatible = "nvidia,tegra20-sflash"; | |
| reg = <0x7000c380 0x80>; | |
| interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; | |
| #address-cells = <1>; | |
| #size-cells = <0>; | |
| clocks = <&tegra_car TEGRA20_CLK_SPI>; | |
| resets = <&tegra_car 43>; | |
| reset-names = "spi"; | |
| dmas = <&apbdma 11>, <&apbdma 11>; | |
| dma-names = "rx", "tx"; | |
| status = "disabled"; | |
| }; | |
| i2c2: i2c@7000c400 { | |
| compatible = "nvidia,tegra20-i2c"; | |
| reg = <0x7000c400 0x100>; | |
| interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; | |
| #address-cells = <1>; | |
| #size-cells = <0>; | |
| clocks = <&tegra_car TEGRA20_CLK_I2C2>, | |
| <&tegra_car TEGRA20_CLK_PLL_P_OUT3>; | |
| clock-names = "div-clk", "fast-clk"; | |
| resets = <&tegra_car 54>; | |
| reset-names = "i2c"; | |
| dmas = <&apbdma 22>, <&apbdma 22>; | |
| dma-names = "rx", "tx"; | |
| status = "disabled"; | |
| }; | |
| i2c@7000c500 { | |
| compatible = "nvidia,tegra20-i2c"; | |
| reg = <0x7000c500 0x100>; | |
| interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; | |
| #address-cells = <1>; | |
| #size-cells = <0>; | |
| clocks = <&tegra_car TEGRA20_CLK_I2C3>, | |
| <&tegra_car TEGRA20_CLK_PLL_P_OUT3>; | |
| clock-names = "div-clk", "fast-clk"; | |
| resets = <&tegra_car 67>; | |
| reset-names = "i2c"; | |
| dmas = <&apbdma 23>, <&apbdma 23>; | |
| dma-names = "rx", "tx"; | |
| status = "disabled"; | |
| }; | |
| i2c@7000d000 { | |
| compatible = "nvidia,tegra20-i2c-dvc"; | |
| reg = <0x7000d000 0x200>; | |
| interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; | |
| #address-cells = <1>; | |
| #size-cells = <0>; | |
| clocks = <&tegra_car TEGRA20_CLK_DVC>, | |
| <&tegra_car TEGRA20_CLK_PLL_P_OUT3>; | |
| clock-names = "div-clk", "fast-clk"; | |
| resets = <&tegra_car 47>; | |
| reset-names = "i2c"; | |
| dmas = <&apbdma 24>, <&apbdma 24>; | |
| dma-names = "rx", "tx"; | |
| status = "disabled"; | |
| }; | |
| spi@7000d400 { | |
| compatible = "nvidia,tegra20-slink"; | |
| reg = <0x7000d400 0x200>; | |
| interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; | |
| #address-cells = <1>; | |
| #size-cells = <0>; | |
| clocks = <&tegra_car TEGRA20_CLK_SBC1>; | |
| resets = <&tegra_car 41>; | |
| reset-names = "spi"; | |
| dmas = <&apbdma 15>, <&apbdma 15>; | |
| dma-names = "rx", "tx"; | |
| status = "disabled"; | |
| }; | |
| spi@7000d600 { | |
| compatible = "nvidia,tegra20-slink"; | |
| reg = <0x7000d600 0x200>; | |
| interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; | |
| #address-cells = <1>; | |
| #size-cells = <0>; | |
| clocks = <&tegra_car TEGRA20_CLK_SBC2>; | |
| resets = <&tegra_car 44>; | |
| reset-names = "spi"; | |
| dmas = <&apbdma 16>, <&apbdma 16>; | |
| dma-names = "rx", "tx"; | |
| status = "disabled"; | |
| }; | |
| spi@7000d800 { | |
| compatible = "nvidia,tegra20-slink"; | |
| reg = <0x7000d800 0x200>; | |
| interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; | |
| #address-cells = <1>; | |
| #size-cells = <0>; | |
| clocks = <&tegra_car TEGRA20_CLK_SBC3>; | |
| resets = <&tegra_car 46>; | |
| reset-names = "spi"; | |
| dmas = <&apbdma 17>, <&apbdma 17>; | |
| dma-names = "rx", "tx"; | |
| status = "disabled"; | |
| }; | |
| spi@7000da00 { | |
| compatible = "nvidia,tegra20-slink"; | |
| reg = <0x7000da00 0x200>; | |
| interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; | |
| #address-cells = <1>; | |
| #size-cells = <0>; | |
| clocks = <&tegra_car TEGRA20_CLK_SBC4>; | |
| resets = <&tegra_car 68>; | |
| reset-names = "spi"; | |
| dmas = <&apbdma 18>, <&apbdma 18>; | |
| dma-names = "rx", "tx"; | |
| status = "disabled"; | |
| }; | |
| rtc@7000e000 { | |
| compatible = "nvidia,tegra20-rtc"; | |
| reg = <0x7000e000 0x100>; | |
| interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; | |
| clocks = <&tegra_car TEGRA20_CLK_RTC>; | |
| }; | |
| kbc@7000e200 { | |
| compatible = "nvidia,tegra20-kbc"; | |
| reg = <0x7000e200 0x100>; | |
| interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; | |
| clocks = <&tegra_car TEGRA20_CLK_KBC>; | |
| resets = <&tegra_car 36>; | |
| reset-names = "kbc"; | |
| status = "disabled"; | |
| }; | |
| tegra_pmc: pmc@7000e400 { | |
| compatible = "nvidia,tegra20-pmc"; | |
| reg = <0x7000e400 0x400>; | |
| clocks = <&tegra_car TEGRA20_CLK_PCLK>, <&clk32k_in>; | |
| clock-names = "pclk", "clk32k_in"; | |
| #clock-cells = <1>; | |
| pd_core: core-domain { | |
| #power-domain-cells = <0>; | |
| operating-points-v2 = <&core_opp_table>; | |
| }; | |
| powergates { | |
| pd_mpe: mpe { | |
| clocks = <&tegra_car TEGRA20_CLK_MPE>; | |
| resets = <&mc TEGRA20_MC_RESET_MPEA>, | |
| <&mc TEGRA20_MC_RESET_MPEB>, | |
| <&mc TEGRA20_MC_RESET_MPEC>, | |
| <&tegra_car TEGRA20_CLK_MPE>; | |
| power-domains = <&pd_core>; | |
| #power-domain-cells = <0>; | |
| }; | |
| pd_3d: td { | |
| clocks = <&tegra_car TEGRA20_CLK_GR3D>; | |
| resets = <&mc TEGRA20_MC_RESET_3D>, | |
| <&tegra_car TEGRA20_CLK_GR3D>; | |
| power-domains = <&pd_core>; | |
| #power-domain-cells = <0>; | |
| }; | |
| pd_vde: vdec { | |
| clocks = <&tegra_car TEGRA20_CLK_VDE>; | |
| resets = <&mc TEGRA20_MC_RESET_VDE>, | |
| <&tegra_car TEGRA20_CLK_VDE>; | |
| power-domains = <&pd_core>; | |
| #power-domain-cells = <0>; | |
| }; | |
| pd_venc: venc { | |
| clocks = <&tegra_car TEGRA20_CLK_ISP>, | |
| <&tegra_car TEGRA20_CLK_VI>, | |
| <&tegra_car TEGRA20_CLK_CSI>; | |
| resets = <&mc TEGRA20_MC_RESET_ISP>, | |
| <&mc TEGRA20_MC_RESET_VI>, | |
| <&tegra_car TEGRA20_CLK_ISP>, | |
| <&tegra_car 20 /* VI */>, | |
| <&tegra_car TEGRA20_CLK_CSI>; | |
| power-domains = <&pd_core>; | |
| #power-domain-cells = <0>; | |
| }; | |
| }; | |
| }; | |
| mc: memory-controller@7000f000 { | |
| compatible = "nvidia,tegra20-mc-gart"; | |
| reg = <0x7000f000 0x00000400>, /* controller registers */ | |
| <0x58000000 0x02000000>; /* GART aperture */ | |
| clocks = <&tegra_car TEGRA20_CLK_MC>; | |
| clock-names = "mc"; | |
| interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; | |
| #reset-cells = <1>; | |
| #iommu-cells = <0>; | |
| #interconnect-cells = <1>; | |
| }; | |
| emc: memory-controller@7000f400 { | |
| compatible = "nvidia,tegra20-emc"; | |
| reg = <0x7000f400 0x400>; | |
| interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; | |
| clocks = <&tegra_car TEGRA20_CLK_EMC>; | |
| power-domains = <&pd_core>; | |
| #address-cells = <1>; | |
| #size-cells = <0>; | |
| #interconnect-cells = <0>; | |
| nvidia,memory-controller = <&mc>; | |
| operating-points-v2 = <&emc_icc_dvfs_opp_table>; | |
| }; | |
| fuse@7000f800 { | |
| compatible = "nvidia,tegra20-efuse"; | |
| reg = <0x7000f800 0x400>; | |
| clocks = <&tegra_car TEGRA20_CLK_FUSE>; | |
| clock-names = "fuse"; | |
| resets = <&tegra_car 39>; | |
| reset-names = "fuse"; | |
| }; | |
| pcie@80003000 { | |
| compatible = "nvidia,tegra20-pcie"; | |
| device_type = "pci"; | |
| reg = <0x80003000 0x00000800>, /* PADS registers */ | |
| <0x80003800 0x00000200>, /* AFI registers */ | |
| <0x90000000 0x10000000>; /* configuration space */ | |
| reg-names = "pads", "afi", "cs"; | |
| interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ | |
| <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ | |
| interrupt-names = "intr", "msi"; | |
| #interrupt-cells = <1>; | |
| interrupt-map-mask = <0 0 0 0>; | |
| interrupt-map = <0 0 0 0 &intc GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; | |
| bus-range = <0x00 0xff>; | |
| #address-cells = <3>; | |
| #size-cells = <2>; | |
| ranges = <0x02000000 0 0x80000000 0x80000000 0 0x00001000>, /* port 0 registers */ | |
| <0x02000000 0 0x80001000 0x80001000 0 0x00001000>, /* port 1 registers */ | |
| <0x01000000 0 0 0x82000000 0 0x00010000>, /* downstream I/O */ | |
| <0x02000000 0 0xa0000000 0xa0000000 0 0x08000000>, /* non-prefetchable memory */ | |
| <0x42000000 0 0xa8000000 0xa8000000 0 0x18000000>; /* prefetchable memory */ | |
| clocks = <&tegra_car TEGRA20_CLK_PEX>, | |
| <&tegra_car TEGRA20_CLK_AFI>, | |
| <&tegra_car TEGRA20_CLK_PLL_E>; | |
| clock-names = "pex", "afi", "pll_e"; | |
| resets = <&tegra_car 70>, | |
| <&tegra_car 72>, | |
| <&tegra_car 74>; | |
| reset-names = "pex", "afi", "pcie_x"; | |
| power-domains = <&pd_core>; | |
| operating-points-v2 = <&pcie_dvfs_opp_table>; | |
| status = "disabled"; | |
| pci@1,0 { | |
| device_type = "pci"; | |
| assigned-addresses = <0x82000800 0 0x80000000 0 0x1000>; | |
| reg = <0x000800 0 0 0 0>; | |
| bus-range = <0x00 0xff>; | |
| status = "disabled"; | |
| #address-cells = <3>; | |
| #size-cells = <2>; | |
| ranges; | |
| nvidia,num-lanes = <2>; | |
| }; | |
| pci@2,0 { | |
| device_type = "pci"; | |
| assigned-addresses = <0x82001000 0 0x80001000 0 0x1000>; | |
| reg = <0x001000 0 0 0 0>; | |
| bus-range = <0x00 0xff>; | |
| status = "disabled"; | |
| #address-cells = <3>; | |
| #size-cells = <2>; | |
| ranges; | |
| nvidia,num-lanes = <2>; | |
| }; | |
| }; | |
| usb@c5000000 { | |
| compatible = "nvidia,tegra20-ehci"; | |
| reg = <0xc5000000 0x4000>; | |
| interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; | |
| phy_type = "utmi"; | |
| clocks = <&tegra_car TEGRA20_CLK_USBD>; | |
| resets = <&tegra_car 22>; | |
| reset-names = "usb"; | |
| nvidia,needs-double-reset; | |
| nvidia,phy = <&phy1>; | |
| power-domains = <&pd_core>; | |
| operating-points-v2 = <&usbd_dvfs_opp_table>; | |
| status = "disabled"; | |
| }; | |
| phy1: usb-phy@c5000000 { | |
| compatible = "nvidia,tegra20-usb-phy"; | |
| reg = <0xc5000000 0x4000>, | |
| <0xc5000000 0x4000>; | |
| interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; | |
| phy_type = "utmi"; | |
| clocks = <&tegra_car TEGRA20_CLK_USBD>, | |
| <&tegra_car TEGRA20_CLK_PLL_U>, | |
| <&tegra_car TEGRA20_CLK_CLK_M>, | |
| <&tegra_car TEGRA20_CLK_USBD>; | |
| clock-names = "reg", "pll_u", "timer", "utmi-pads"; | |
| resets = <&tegra_car 22>, <&tegra_car 22>; | |
| reset-names = "usb", "utmi-pads"; | |
| #phy-cells = <0>; | |
| nvidia,has-legacy-mode; | |
| nvidia,hssync-start-delay = <9>; | |
| nvidia,idle-wait-delay = <17>; | |
| nvidia,elastic-limit = <16>; | |
| nvidia,term-range-adj = <6>; | |
| nvidia,xcvr-setup = <9>; | |
| nvidia,xcvr-lsfslew = <1>; | |
| nvidia,xcvr-lsrslew = <1>; | |
| nvidia,has-utmi-pad-registers; | |
| nvidia,pmc = <&tegra_pmc 0>; | |
| status = "disabled"; | |
| }; | |
| usb@c5004000 { | |
| compatible = "nvidia,tegra20-ehci"; | |
| reg = <0xc5004000 0x4000>; | |
| interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; | |
| phy_type = "ulpi"; | |
| clocks = <&tegra_car TEGRA20_CLK_USB2>; | |
| resets = <&tegra_car 58>; | |
| reset-names = "usb"; | |
| nvidia,phy = <&phy2>; | |
| power-domains = <&pd_core>; | |
| operating-points-v2 = <&usb2_dvfs_opp_table>; | |
| status = "disabled"; | |
| }; | |
| phy2: usb-phy@c5004000 { | |
| compatible = "nvidia,tegra20-usb-phy"; | |
| reg = <0xc5004000 0x4000>; | |
| interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; | |
| phy_type = "ulpi"; | |
| clocks = <&tegra_car TEGRA20_CLK_USB2>, | |
| <&tegra_car TEGRA20_CLK_PLL_U>, | |
| <&tegra_car TEGRA20_CLK_CDEV2>; | |
| clock-names = "reg", "pll_u", "ulpi-link"; | |
| resets = <&tegra_car 58>, <&tegra_car 22>; | |
| reset-names = "usb", "utmi-pads"; | |
| #phy-cells = <0>; | |
| nvidia,pmc = <&tegra_pmc 1>; | |
| status = "disabled"; | |
| }; | |
| usb@c5008000 { | |
| compatible = "nvidia,tegra20-ehci"; | |
| reg = <0xc5008000 0x4000>; | |
| interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; | |
| phy_type = "utmi"; | |
| clocks = <&tegra_car TEGRA20_CLK_USB3>; | |
| resets = <&tegra_car 59>; | |
| reset-names = "usb"; | |
| nvidia,phy = <&phy3>; | |
| power-domains = <&pd_core>; | |
| operating-points-v2 = <&usb3_dvfs_opp_table>; | |
| status = "disabled"; | |
| }; | |
| phy3: usb-phy@c5008000 { | |
| compatible = "nvidia,tegra20-usb-phy"; | |
| reg = <0xc5008000 0x4000>, | |
| <0xc5000000 0x4000>; | |
| interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; | |
| phy_type = "utmi"; | |
| clocks = <&tegra_car TEGRA20_CLK_USB3>, | |
| <&tegra_car TEGRA20_CLK_PLL_U>, | |
| <&tegra_car TEGRA20_CLK_CLK_M>, | |
| <&tegra_car TEGRA20_CLK_USBD>; | |
| clock-names = "reg", "pll_u", "timer", "utmi-pads"; | |
| resets = <&tegra_car 59>, <&tegra_car 22>; | |
| reset-names = "usb", "utmi-pads"; | |
| #phy-cells = <0>; | |
| nvidia,hssync-start-delay = <9>; | |
| nvidia,idle-wait-delay = <17>; | |
| nvidia,elastic-limit = <16>; | |
| nvidia,term-range-adj = <6>; | |
| nvidia,xcvr-setup = <9>; | |
| nvidia,xcvr-lsfslew = <2>; | |
| nvidia,xcvr-lsrslew = <2>; | |
| nvidia,pmc = <&tegra_pmc 2>; | |
| status = "disabled"; | |
| }; | |
| mmc@c8000000 { | |
| compatible = "nvidia,tegra20-sdhci"; | |
| reg = <0xc8000000 0x200>; | |
| interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; | |
| clocks = <&tegra_car TEGRA20_CLK_SDMMC1>; | |
| clock-names = "sdhci"; | |
| resets = <&tegra_car 14>; | |
| reset-names = "sdhci"; | |
| power-domains = <&pd_core>; | |
| operating-points-v2 = <&sdmmc1_dvfs_opp_table>; | |
| status = "disabled"; | |
| }; | |
| mmc@c8000200 { | |
| compatible = "nvidia,tegra20-sdhci"; | |
| reg = <0xc8000200 0x200>; | |
| interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; | |
| clocks = <&tegra_car TEGRA20_CLK_SDMMC2>; | |
| clock-names = "sdhci"; | |
| resets = <&tegra_car 9>; | |
| reset-names = "sdhci"; | |
| power-domains = <&pd_core>; | |
| operating-points-v2 = <&sdmmc2_dvfs_opp_table>; | |
| status = "disabled"; | |
| }; | |
| mmc@c8000400 { | |
| compatible = "nvidia,tegra20-sdhci"; | |
| reg = <0xc8000400 0x200>; | |
| interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; | |
| clocks = <&tegra_car TEGRA20_CLK_SDMMC3>; | |
| clock-names = "sdhci"; | |
| resets = <&tegra_car 69>; | |
| reset-names = "sdhci"; | |
| power-domains = <&pd_core>; | |
| operating-points-v2 = <&sdmmc3_dvfs_opp_table>; | |
| status = "disabled"; | |
| }; | |
| mmc@c8000600 { | |
| compatible = "nvidia,tegra20-sdhci"; | |
| reg = <0xc8000600 0x200>; | |
| interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; | |
| clocks = <&tegra_car TEGRA20_CLK_SDMMC4>; | |
| clock-names = "sdhci"; | |
| resets = <&tegra_car 15>; | |
| reset-names = "sdhci"; | |
| power-domains = <&pd_core>; | |
| operating-points-v2 = <&sdmmc4_dvfs_opp_table>; | |
| status = "disabled"; | |
| }; | |
| cpus { | |
| #address-cells = <1>; | |
| #size-cells = <0>; | |
| cpu@0 { | |
| device_type = "cpu"; | |
| compatible = "arm,cortex-a9"; | |
| reg = <0>; | |
| clocks = <&tegra_car TEGRA20_CLK_CCLK>; | |
| }; | |
| cpu@1 { | |
| device_type = "cpu"; | |
| compatible = "arm,cortex-a9"; | |
| reg = <1>; | |
| clocks = <&tegra_car TEGRA20_CLK_CCLK>; | |
| }; | |
| }; | |
| pmu { | |
| compatible = "arm,cortex-a9-pmu"; | |
| interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, | |
| <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; | |
| interrupt-affinity = <&{/cpus/cpu@0}>, | |
| <&{/cpus/cpu@1}>; | |
| }; | |
| sound-hdmi { | |
| compatible = "simple-audio-card"; | |
| simple-audio-card,name = "NVIDIA Tegra20 HDMI"; | |
| #address-cells = <1>; | |
| #size-cells = <0>; | |
| simple-audio-card,dai-link@0 { | |
| reg = <0>; | |
| codec { | |
| sound-dai = <&tegra_hdmi>; | |
| }; | |
| cpu { | |
| sound-dai = <&tegra_spdif>; | |
| }; | |
| }; | |
| }; | |
| }; |