| /* SPDX-License-Identifier: GPL-2.0+ */ |
| /* |
| * Copyright 2018 NXP |
| */ |
| |
| #ifndef __IMX8M_EVK_H |
| #define __IMX8M_EVK_H |
| |
| #include <linux/sizes.h> |
| #include <linux/stringify.h> |
| #include <asm/arch/imx-regs.h> |
| |
| #ifdef CONFIG_XPL_BUILD |
| /*#define CONFIG_ENABLE_DDR_TRAINING_DEBUG*/ |
| |
| /* malloc f used before GD_FLG_FULL_MALLOC_INIT set */ |
| #define CFG_MALLOC_F_ADDR 0x182000 |
| /* For RAW image gives a error info not panic */ |
| |
| #define CFG_POWER_PFUZE100_I2C_ADDR 0x08 |
| #endif |
| |
| /* ENET Config */ |
| /* ENET1 */ |
| #if defined(CONFIG_CMD_NET) |
| #define CFG_FEC_MXC_PHYADDR 0 |
| #endif |
| |
| /* Link Definitions */ |
| |
| #define CFG_SYS_INIT_RAM_ADDR 0x40000000 |
| #define CFG_SYS_INIT_RAM_SIZE 0x80000 |
| |
| #define CFG_SYS_SDRAM_BASE 0x40000000 |
| #define PHYS_SDRAM 0x40000000 |
| #define PHYS_SDRAM_SIZE 0xC0000000 /* 3GB DDR */ |
| |
| #define CFG_MXC_UART_BASE UART_BASE_ADDR(1) |
| |
| #define CFG_SYS_FSL_USDHC_NUM 2 |
| #define CFG_SYS_FSL_ESDHC_ADDR 0 |
| |
| #endif |
