| /* | |
| * (C) Copyright 2000 | |
| * Sysgo Real-Time Solutions, GmbH <www.elinos.com> | |
| * Marius Groeger <mgroeger@sysgo.de> | |
| * | |
| * Configuation settings for the MBX8xx board. | |
| * | |
| * ----------------------------------------------------------------- | |
| * See file CREDITS for list of people who contributed to this | |
| * project. | |
| * | |
| * This program is free software; you can redistribute it and/or | |
| * modify it under the terms of the GNU General Public License as | |
| * published by the Free Software Foundation; either version 2 of | |
| * the License, or (at your option) any later version. | |
| * | |
| * This program is distributed in the hope that it will be useful, | |
| * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| * GNU General Public License for more details. | |
| * | |
| * You should have received a copy of the GNU General Public License | |
| * along with this program; if not, write to the Free Software | |
| * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
| * MA 02111-1307 USA | |
| */ | |
| /* | |
| * Changed 2002-10-01 | |
| * Added PCMCIA defines mostly taken from other U-Boot boards that | |
| * have PCMCIA already working. If you find any bugs, incorrect assumptions | |
| * feel free to fix them yourself and submit a patch. | |
| * Rod Boyce <rod_boyce@stratexnet.com. | |
| */ | |
| /* | |
| * board/config.h - configuration options, board specific | |
| */ | |
| #ifndef __CONFIG_H | |
| #define __CONFIG_H | |
| /* | |
| * High Level Configuration Options | |
| * (easy to change) | |
| */ | |
| #define CONFIG_MPC860 1 /* This is a MPC860 CPU */ | |
| #define CONFIG_MBX 1 /* ...on an MBX module */ | |
| #define CONFIG_SYS_TEXT_BASE 0xfe000000 | |
| #define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ | |
| #undef CONFIG_8xx_CONS_SMC2 | |
| #undef CONFIG_8xx_CONS_NONE | |
| #define CONFIG_BAUDRATE 9600 | |
| /* Define this to use the PCI bus */ | |
| #undef CONFIG_USE_PCI | |
| #define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */ | |
| #define CONFIG_8xx_GCLK_FREQ (50000000UL) | |
| #if 1 | |
| #define CONFIG_BOOTDELAY -1 /* autoboot disabled */ | |
| #else | |
| #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ | |
| #endif | |
| #define CONFIG_BOOTCOMMAND "bootm 20000" /* autoboot command */ | |
| #define CONFIG_BOOTARGS "root=/dev/nfs rw " \ | |
| "nfsroot=10.0.0.2:/opt/eldk/ppc_8xx " \ | |
| "nfsaddrs=10.0.0.99:10.0.0.2" | |
| #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ | |
| #undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ | |
| #undef CONFIG_WATCHDOG /* watchdog disabled */ | |
| /* | |
| * BOOTP options | |
| */ | |
| #define CONFIG_BOOTP_BOOTFILESIZE | |
| #define CONFIG_BOOTP_BOOTPATH | |
| #define CONFIG_BOOTP_GATEWAY | |
| #define CONFIG_BOOTP_HOSTNAME | |
| /* | |
| * Command line configuration. | |
| */ | |
| #define CONFIG_CMD_NET | |
| #define CONFIG_CMD_SDRAM | |
| #define CONFIG_CMD_PCMCIA | |
| #define CONFIG_CMD_IDE | |
| #define CONFIG_DOS_PARTITION | |
| /* | |
| * Miscellaneous configurable options | |
| */ | |
| #define CONFIG_SYS_LONGHELP /* undef to save memory */ | |
| #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ | |
| #undef CONFIG_SYS_HUSH_PARSER /* Hush parse for U-Boot */ | |
| #if defined(CONFIG_CMD_KGDB) | |
| #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ | |
| #else | |
| #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ | |
| #endif | |
| #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ | |
| #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
| #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
| #define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ | |
| #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ | |
| #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ | |
| #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ | |
| /* | |
| * Low Level Configuration Settings | |
| * (address mappings, register initial values, etc.) | |
| * You should know what you are doing if you make changes here. | |
| */ | |
| /*----------------------------------------------------------------------- | |
| * Physical memory map as defined by the MBX PGM | |
| */ | |
| #define CONFIG_SYS_IMMR 0xFA200000 /* Internal Memory Mapped Register*/ | |
| #define CONFIG_SYS_NVRAM_BASE 0xFA000000 /* NVRAM */ | |
| #define CONFIG_SYS_NVRAM_OR 0xffe00000 /* w/o speed dependent flags!! */ | |
| #define CONFIG_SYS_CSR_BASE 0xFA100000 /* Control/Status Registers */ | |
| #define CONFIG_SYS_PCIMEM_BASE 0x80000000 /* PCI I/O and Memory Spaces */ | |
| #define CONFIG_SYS_PCIMEM_OR 0xA0000108 | |
| #define CONFIG_SYS_PCIBRIDGE_BASE 0xFA210000 /* PCI-Bus Bridge Registers */ | |
| #define CONFIG_SYS_PCIBRIDGE_OR 0xFFFF0108 | |
| /*----------------------------------------------------------------------- | |
| * Definitions for initial stack pointer and data area (in DPRAM) | |
| */ | |
| #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR | |
| #define CONFIG_SYS_INIT_RAM_SIZE 0x2f00 /* Size of used area in DPRAM */ | |
| #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) | |
| #define CONFIG_SYS_INIT_VPD_SIZE 256 /* size in bytes reserved for vpd buffer */ | |
| #define CONFIG_SYS_INIT_VPD_OFFSET (CONFIG_SYS_GBL_DATA_OFFSET - CONFIG_SYS_INIT_VPD_SIZE) | |
| #define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_VPD_OFFSET-8) | |
| /*----------------------------------------------------------------------- | |
| * Offset in DPMEM where we keep the VPD data | |
| */ | |
| #define CONFIG_SYS_DPRAMVPD (CONFIG_SYS_INIT_VPD_OFFSET - 0x2000) | |
| /*----------------------------------------------------------------------- | |
| * Start addresses for the final memory configuration | |
| * (Set up by the startup code) | |
| * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 | |
| */ | |
| #define CONFIG_SYS_SDRAM_BASE 0x00000000 | |
| #define CONFIG_SYS_FLASH_BASE 0xfe000000 | |
| #ifdef DEBUG | |
| #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ | |
| #else | |
| #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ | |
| #endif | |
| #undef CONFIG_SYS_MONITOR_BASE /* 0x200000 to run U-Boot from RAM */ | |
| #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE | |
| #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ | |
| /* | |
| * For booting Linux, the board info and command line data | |
| * have to be in the first 8 MB of memory, since this is | |
| * the maximum mapped by the Linux kernel during initialization. | |
| */ | |
| #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ | |
| /*----------------------------------------------------------------------- | |
| * FLASH organization | |
| */ | |
| #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ | |
| #define CONFIG_SYS_MAX_FLASH_SECT 16 /* max number of sectors on one chip */ | |
| #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ | |
| #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ | |
| /*----------------------------------------------------------------------- | |
| * NVRAM Configuration | |
| * | |
| * Note: the MBX is special because there is already a firmware on this | |
| * board: EPPC-Bug from Motorola. To avoid collisions in NVRAM Usage, we | |
| * access the NVRAM at the offset 0x1000. | |
| */ | |
| #define CONFIG_ENV_IS_IN_NVRAM 1 /* turn on NVRAM env feature */ | |
| #define CONFIG_ENV_ADDR (CONFIG_SYS_NVRAM_BASE + 0x1000) | |
| #define CONFIG_ENV_SIZE 0x1000 | |
| /*----------------------------------------------------------------------- | |
| * Cache Configuration | |
| */ | |
| #define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ | |
| #if defined(CONFIG_CMD_KGDB) | |
| #define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ | |
| #endif | |
| /*----------------------------------------------------------------------- | |
| * SYPCR - System Protection Control 11-9 | |
| * SYPCR can only be written once after reset! | |
| *----------------------------------------------------------------------- | |
| * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze | |
| */ | |
| #if defined(CONFIG_WATCHDOG) | |
| #define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ | |
| SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) | |
| #else | |
| #define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF) | |
| #endif | |
| /*----------------------------------------------------------------------- | |
| * SIUMCR - SIU Module Configuration 11-6 | |
| *----------------------------------------------------------------------- | |
| * PCMCIA config., multi-function pin tri-state | |
| */ | |
| /* #define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DPC | SIUMCR_MLRC10 | SIUMCR_SEME) */ | |
| #define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DPC | SIUMCR_MLRC11 | SIUMCR_SEME | SIUMCR_BSC ) | |
| /*----------------------------------------------------------------------- | |
| * TBSCR - Time Base Status and Control 11-26 | |
| *----------------------------------------------------------------------- | |
| * Clear Reference Interrupt Status, Timebase freezing enabled | |
| */ | |
| #define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) | |
| /*----------------------------------------------------------------------- | |
| * PISCR - Periodic Interrupt Status and Control 11-31 | |
| *----------------------------------------------------------------------- | |
| * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled | |
| */ | |
| #define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF | PISCR_PTE) | |
| /*----------------------------------------------------------------------- | |
| * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 | |
| *----------------------------------------------------------------------- | |
| * Reset PLL lock status sticky bit, timer expired status bit and timer | |
| * interrupt status bit - leave PLL multiplication factor unchanged ! | |
| */ | |
| #define CONFIG_SYS_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) | |
| /*----------------------------------------------------------------------- | |
| * SCCR - System Clock and reset Control Register 15-27 | |
| *----------------------------------------------------------------------- | |
| * Set clock output, timebase and RTC source and divider, | |
| * power management and some other internal clocks | |
| */ | |
| #define SCCR_MASK (SCCR_RTDIV | SCCR_RTSEL) | |
| #define CONFIG_SYS_SCCR SCCR_TBS | |
| /*----------------------------------------------------------------------- | |
| * PCMCIA stuff | |
| *----------------------------------------------------------------------- | |
| * | |
| */ | |
| #define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000) | |
| #define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 ) | |
| #define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000) | |
| #define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 ) | |
| #define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000) | |
| #define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 ) | |
| #define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000) | |
| #define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 ) | |
| #define CONFIG_SYS_PCMCIA_INTERRUPT SIU_LEVEL6 | |
| #define CONFIG_PCMCIA_SLOT_A 1 | |
| /*----------------------------------------------------------------------- | |
| * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) | |
| *----------------------------------------------------------------------- | |
| */ | |
| #define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ | |
| #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ | |
| #undef CONFIG_IDE_LED /* LED for ide not supported */ | |
| #undef CONFIG_IDE_RESET /* reset for ide not supported */ | |
| #define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ | |
| #define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ | |
| #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 | |
| #define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR | |
| /* Offset for data I/O */ | |
| #define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) | |
| /* Offset for normal register accesses */ | |
| #define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) | |
| /* Offset for alternate registers */ | |
| #define CONFIG_SYS_ATA_ALT_OFFSET 0x0100 | |
| /*----------------------------------------------------------------------- | |
| * Debug Entry Mode | |
| *----------------------------------------------------------------------- | |
| * | |
| */ | |
| #define CONFIG_SYS_DER 0 | |
| #endif /* __CONFIG_H */ |