| /* | |
| * (C) Copyright 2000 | |
| * Wolfgang Denk, DENX Software Engineering, wd@denx.de. | |
| * | |
| * See file CREDITS for list of people who contributed to this | |
| * project. | |
| * | |
| * This program is free software; you can redistribute it and/or | |
| * modify it under the terms of the GNU General Public License as | |
| * published by the Free Software Foundation; either version 2 of | |
| * the License, or (at your option) any later version. | |
| * | |
| * This program is distributed in the hope that it will be useful, | |
| * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| * GNU General Public License for more details. | |
| * | |
| * You should have received a copy of the GNU General Public License | |
| * along with this program; if not, write to the Free Software | |
| * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
| * MA 02111-1307 USA | |
| */ | |
| /* | |
| * board/config.h - configuration options, board specific | |
| */ | |
| #ifndef __CONFIG_H | |
| #define __CONFIG_H | |
| /* | |
| * High Level Configuration Options | |
| * (easy to change) | |
| */ | |
| #define CONFIG_MPC823 1 /* This is a MPC823 CPU */ | |
| #define CONFIG_MVS 1 /* ...on a MVsensor module */ | |
| #define CONFIG_MVS_16BIT_FLASH /* ...with 16-bit flash access */ | |
| #define CONFIG_8xx_GCLK_FREQ 50000000/* ... and a 50 MHz CPU */ | |
| #define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */ | |
| #undef CONFIG_8xx_CONS_SMC1 /* Console is *NOT* on SMC1 */ | |
| #define CONFIG_8xx_CONS_SMC2 1 /* Console is on SMC2 */ | |
| #undef CONFIG_8xx_CONS_NONE | |
| #define CONFIG_BAUDRATE 115200 /* console baudrate */ | |
| #define CONFIG_BOOTDELAY 5 /* autoboot after this many seconds */ | |
| #define CONFIG_PREBOOT "echo;" \ | |
| "echo To mount root over NFS use \"run bootnet\";" \ | |
| "echo To mount root from FLASH use \"run bootflash\";" \ | |
| "echo" | |
| #define CONFIG_BOOTARGS "root=/dev/mtdblock2 rw" | |
| #define CONFIG_BOOTCOMMAND \ | |
| "bootp; " \ | |
| "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ | |
| "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \ | |
| "bootm" | |
| #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ | |
| #undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ | |
| #define CONFIG_WATCHDOG /* watchdog disabled/enabled */ | |
| #undef CONFIG_STATUS_LED /* Status LED disabled/enabled */ | |
| #undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ | |
| /* | |
| * BOOTP options | |
| */ | |
| #define CONFIG_BOOTP_SUBNETMASK | |
| #define CONFIG_BOOTP_GATEWAY | |
| #define CONFIG_BOOTP_HOSTNAME | |
| #define CONFIG_BOOTP_BOOTPATH | |
| #define CONFIG_BOOTP_VENDOREX | |
| #undef CONFIG_MAC_PARTITION | |
| #undef CONFIG_DOS_PARTITION | |
| #define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ | |
| /* | |
| * Command line configuration. | |
| */ | |
| #define CONFIG_CMD_LOADS | |
| #define CONFIG_CMD_LOADB | |
| #define CONFIG_CMD_IMI | |
| #define CONFIG_CMD_FLASH | |
| #define CONFIG_CMD_MEMORY | |
| #define CONFIG_CMD_NET | |
| #define CONFIG_CMD_DHCP | |
| #define CONFIG_CMD_SAVEENV | |
| #define CONFIG_CMD_BOOTD | |
| #define CONFIG_CMD_RUN | |
| /* | |
| * Miscellaneous configurable options | |
| */ | |
| #undef CONFIG_SYS_LONGHELP /* undef to save memory */ | |
| #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ | |
| #undef CONFIG_SYS_HUSH_PARSER /* Hush parse for U-Boot ?? */ | |
| #if defined(CONFIG_CMD_KGDB) | |
| #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ | |
| #else | |
| #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ | |
| #endif | |
| #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ | |
| #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
| #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
| #define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ | |
| #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ | |
| #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ | |
| #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ | |
| /* | |
| * Low Level Configuration Settings | |
| * (address mappings, register initial values, etc.) | |
| * You should know what you are doing if you make changes here. | |
| */ | |
| /*----------------------------------------------------------------------- | |
| * Internal Memory Mapped Register | |
| */ | |
| #define CONFIG_SYS_IMMR 0xFFF00000 | |
| /*----------------------------------------------------------------------- | |
| * Definitions for initial stack pointer and data area (in DPRAM) | |
| */ | |
| #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR | |
| #define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */ | |
| #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) | |
| #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET | |
| /*----------------------------------------------------------------------- | |
| * Start addresses for the final memory configuration | |
| * (Set up by the startup code) | |
| * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 | |
| */ | |
| #define CONFIG_SYS_SDRAM_BASE 0x00000000 | |
| #define CONFIG_SYS_FLASH_BASE 0x40000000 | |
| #define CONFIG_SYS_MONITOR_LEN (128 << 10) /* Reserve 192 kB for Monitor */ | |
| #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE | |
| #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ | |
| /* | |
| * For booting Linux, the board info and command line data | |
| * have to be in the first 8 MB of memory, since this is | |
| * the maximum mapped by the Linux kernel during initialization. | |
| */ | |
| #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ | |
| /*----------------------------------------------------------------------- | |
| * FLASH organization | |
| */ | |
| #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ | |
| #define CONFIG_SYS_MAX_FLASH_SECT 71 /* max number of sectors on one chip (for AMD320DB chip) */ | |
| #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ | |
| #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ | |
| #define CONFIG_ENV_IS_IN_FLASH 1 | |
| /* 4MB flash - use bottom sectors of a bottom boot sector flash (16 bit access) */ | |
| #define CONFIG_ENV_OFFSET 0x8000 /* Offset of Environment Sector (bottom boot sector) */ | |
| #define CONFIG_ENV_SIZE 0x2000 /* Used Size of Environment Sector 8k */ | |
| /*----------------------------------------------------------------------- | |
| * Cache Configuration | |
| */ | |
| #define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ | |
| #if defined(CONFIG_CMD_KGDB) | |
| #define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ | |
| #endif | |
| /*----------------------------------------------------------------------- | |
| * SYPCR - System Protection Control 11-9 | |
| * SYPCR can only be written once after reset! | |
| *----------------------------------------------------------------------- | |
| * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze | |
| */ | |
| #if defined(CONFIG_WATCHDOG) | |
| #define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ | |
| SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) | |
| #else | |
| #define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) | |
| #endif | |
| /*----------------------------------------------------------------------- | |
| * SIUMCR - SIU Module Configuration 11-6 | |
| *----------------------------------------------------------------------- | |
| * PCMCIA config., multi-function pin tri-state | |
| */ | |
| #define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) | |
| /*----------------------------------------------------------------------- | |
| * TBSCR - Time Base Status and Control 11-26 | |
| *----------------------------------------------------------------------- | |
| * Clear Reference Interrupt Status, Timebase freezing enabled | |
| */ | |
| #define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) | |
| /*----------------------------------------------------------------------- | |
| * RTCSC - Real-Time Clock Status and Control Register 11-27 | |
| *----------------------------------------------------------------------- | |
| */ | |
| #define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) | |
| /*----------------------------------------------------------------------- | |
| * PISCR - Periodic Interrupt Status and Control 11-31 | |
| *----------------------------------------------------------------------- | |
| * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled | |
| */ | |
| #define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF) | |
| /*----------------------------------------------------------------------- | |
| * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 | |
| *----------------------------------------------------------------------- | |
| * Reset PLL lock status sticky bit, timer expired status bit and timer | |
| * interrupt status bit | |
| * | |
| */ | |
| #define CONFIG_SYS_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) | |
| /*----------------------------------------------------------------------- | |
| * SCCR - System Clock and reset Control Register 15-27 | |
| *----------------------------------------------------------------------- | |
| * Set clock output, timebase and RTC source and divider, | |
| * power management and some other internal clocks | |
| */ | |
| #define SCCR_MASK SCCR_EBDF11 | |
| #define CONFIG_SYS_SCCR (SCCR_TBS | \ | |
| SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ | |
| SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ | |
| SCCR_DFALCD00) | |
| /*----------------------------------------------------------------------- | |
| * PCMCIA stuff | |
| *----------------------------------------------------------------------- | |
| * | |
| */ | |
| #define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000) | |
| #define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 ) | |
| #define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000) | |
| #define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 ) | |
| #define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000) | |
| #define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 ) | |
| #define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000) | |
| #define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 ) | |
| /*----------------------------------------------------------------------- | |
| * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) | |
| *----------------------------------------------------------------------- | |
| */ | |
| #define CONFIG_IDE_PCCARD 0 /* **DON'T** Use IDE with PC Card Adapter */ | |
| #undef CONFIG_IDE_PCMCIA /* Direct IDE not supported */ | |
| #undef CONFIG_IDE_LED /* LED for ide not supported */ | |
| #undef CONFIG_IDE_RESET /* reset for ide not supported */ | |
| #define CONFIG_SYS_IDE_MAXBUS 0 /* max. no. of IDE buses */ | |
| #define CONFIG_SYS_IDE_MAXDEVICE 0 /* max. no. of drives per IDE bus */ | |
| #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 | |
| #define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR | |
| /* Offset for data I/O */ | |
| #define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) | |
| /* Offset for normal register accesses */ | |
| #define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) | |
| /* Offset for alternate registers */ | |
| #define CONFIG_SYS_ATA_ALT_OFFSET 0x0100 | |
| /*----------------------------------------------------------------------- | |
| * | |
| *----------------------------------------------------------------------- | |
| * | |
| */ | |
| /*#define CONFIG_SYS_DER 0x2002000F*/ | |
| #define CONFIG_SYS_DER 0 | |
| /* | |
| * Init Memory Controller: | |
| * | |
| * BR0/1 and OR0/1 (FLASH) | |
| */ | |
| #define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ | |
| #undef FLASH_BASE1_PRELIM | |
| /* used to re-map FLASH both when starting from SRAM or FLASH: | |
| * restrict access enough to keep SRAM working (if any) | |
| * but not too much to meddle with FLASH accesses | |
| */ | |
| #define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */ | |
| #define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ | |
| /* | |
| * FLASH timing: | |
| */ | |
| /* 50 MHz CPU - 50 MHz bus: ACS = 00, TRLX = 1, CSNT = 1, SCY = 2, EHTR = 1 */ | |
| #define CONFIG_SYS_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \ | |
| OR_SCY_2_CLK | OR_EHTR | OR_BI) | |
| /* FLASH timing: ACS = 11, TRLX = 0, CSNT = 1, SCY = 5, EHTR = 1 */ | |
| /* | |
| #define CONFIG_SYS_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_DIV2 | OR_BI | \ | |
| OR_SCY_5_CLK | OR_EHTR) | |
| */ | |
| #define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) | |
| #define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) | |
| #ifdef CONFIG_MVS_16BIT_FLASH | |
| #define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V ) | |
| #else | |
| #define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_32 | BR_V ) | |
| #endif | |
| #undef CONFIG_SYS_OR1_REMAP | |
| #undef CONFIG_SYS_OR1_PRELIM | |
| #undef CONFIG_SYS_BR1_PRELIM | |
| /* | |
| * BR2/3 and OR2/3 (SDRAM) | |
| * | |
| */ | |
| #define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */ | |
| #undef SDRAM_BASE3_PRELIM | |
| #define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */ | |
| /* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ | |
| #define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00 | |
| #define CONFIG_SYS_OR2_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM ) | |
| #define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) | |
| #undef CONFIG_SYS_OR3_PRELIM | |
| #undef CONFIG_SYS_BR3_PRELIM | |
| /* | |
| * Memory Periodic Timer Prescaler | |
| * | |
| * The Divider for PTA (refresh timer) configuration is based on an | |
| * example SDRAM configuration (64 MBit, one bank). The adjustment to | |
| * the number of chip selects (NCS) and the actually needed refresh | |
| * rate is done by setting MPTPR. | |
| * | |
| * PTA is calculated from | |
| * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS) | |
| * | |
| * gclk CPU clock (not bus clock!) | |
| * Trefresh Refresh cycle * 4 (four word bursts used) | |
| * | |
| * 4096 Rows from SDRAM example configuration | |
| * 1000 factor s -> ms | |
| * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration | |
| * 4 Number of refresh cycles per period | |
| * 64 Refresh cycle in ms per number of rows | |
| * -------------------------------------------- | |
| * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000 | |
| * | |
| * 50 MHz => 50.000.000 / Divider = 98 | |
| * 66 Mhz => 66.000.000 / Divider = 129 | |
| * 80 Mhz => 80.000.000 / Divider = 156 | |
| */ | |
| #define CONFIG_SYS_MAMR_PTA 98 | |
| /* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit */ | |
| #define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ | |
| #define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ | |
| /* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ | |
| #define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ | |
| #define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ | |
| /* | |
| * MAMR settings for SDRAM | |
| */ | |
| /* 8 column SDRAM */ | |
| #define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ | |
| MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ | |
| MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) | |
| /* 9 column SDRAM */ | |
| #define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ | |
| MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A7 | \ | |
| MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) | |
| #endif /* __CONFIG_H */ |