| /* | |
| * Copyright (C) 2008, Guennadi Liakhovetski <lg@denx.de> | |
| * | |
| * Configuration settings for the MX31ADS Freescale board. | |
| * | |
| * This program is free software; you can redistribute it and/or | |
| * modify it under the terms of the GNU General Public License as | |
| * published by the Free Software Foundation; either version 2 of | |
| * the License, or (at your option) any later version. | |
| * | |
| * This program is distributed in the hope that it will be useful, | |
| * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| * GNU General Public License for more details. | |
| * | |
| * You should have received a copy of the GNU General Public License | |
| * along with this program; if not, write to the Free Software | |
| * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
| * MA 02111-1307 USA | |
| */ | |
| #ifndef __CONFIG_H | |
| #define __CONFIG_H | |
| #include <asm/arch/imx-regs.h> | |
| /* High Level Configuration Options */ | |
| #define CONFIG_ARM1136 1 /* This is an arm1136 CPU core */ | |
| #define CONFIG_MX31 1 /* in a mx31 */ | |
| #define CONFIG_MX31_HCLK_FREQ 26000000 /* RedBoot says 26MHz */ | |
| #define CONFIG_MX31_CLK32 32768 | |
| #define CONFIG_DISPLAY_CPUINFO | |
| #define CONFIG_DISPLAY_BOARDINFO | |
| #define CONFIG_SYS_TEXT_BASE 0xA0000000 | |
| #define CONFIG_MACH_TYPE MACH_TYPE_MX31ADS | |
| /* | |
| * Disabled for now due to build problems under Debian and a significant increase | |
| * in the final file size: 144260 vs. 109536 Bytes. | |
| */ | |
| #if 0 | |
| #define CONFIG_OF_LIBFDT 1 | |
| #define CONFIG_FIT 1 | |
| #define CONFIG_FIT_VERBOSE 1 | |
| #endif | |
| #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ | |
| #define CONFIG_SETUP_MEMORY_TAGS 1 | |
| #define CONFIG_INITRD_TAG 1 | |
| /* | |
| * Size of malloc() pool | |
| */ | |
| #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128 * 1024) | |
| /* | |
| * Hardware drivers | |
| */ | |
| #define CONFIG_MXC_UART | |
| #define CONFIG_MXC_UART_BASE UART1_BASE | |
| #define CONFIG_HARD_SPI 1 | |
| #define CONFIG_MXC_SPI 1 | |
| #define CONFIG_DEFAULT_SPI_BUS 1 | |
| #define CONFIG_DEFAULT_SPI_MODE (SPI_MODE_0 | SPI_CS_HIGH) | |
| #define CONFIG_MXC_GPIO | |
| /* PMIC Controller */ | |
| #define CONFIG_PMIC | |
| #define CONFIG_PMIC_SPI | |
| #define CONFIG_PMIC_FSL | |
| #define CONFIG_FSL_PMIC_BUS 1 | |
| #define CONFIG_FSL_PMIC_CS 0 | |
| #define CONFIG_FSL_PMIC_CLK 1000000 | |
| #define CONFIG_FSL_PMIC_MODE (SPI_MODE_0 | SPI_CS_HIGH) | |
| #define CONFIG_FSL_PMIC_BITLEN 32 | |
| #define CONFIG_RTC_MC13XXX | |
| /* allow to overwrite serial and ethaddr */ | |
| #define CONFIG_ENV_OVERWRITE | |
| #define CONFIG_CONS_INDEX 1 | |
| #define CONFIG_BAUDRATE 115200 | |
| /*********************************************************** | |
| * Command definition | |
| ***********************************************************/ | |
| #include <config_cmd_default.h> | |
| #define CONFIG_CMD_PING | |
| #define CONFIG_CMD_DHCP | |
| #define CONFIG_CMD_SPI | |
| #define CONFIG_CMD_DATE | |
| #define CONFIG_BOOTDELAY 3 | |
| #define CONFIG_LOADADDR 0x80800000 /* loadaddr env var */ | |
| #define CONFIG_EXTRA_ENV_SETTINGS \ | |
| "netdev=eth0\0" \ | |
| "uboot_addr=0xa0000000\0" \ | |
| "uboot=mx31ads/u-boot.bin\0" \ | |
| "kernel=mx31ads/uImage\0" \ | |
| "nfsroot=/opt/eldk/arm\0" \ | |
| "bootargs_base=setenv bootargs console=ttymxc0,115200\0" \ | |
| "bootargs_nfs=setenv bootargs ${bootargs} root=/dev/nfs " \ | |
| "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ | |
| "bootcmd=run bootcmd_net\0" \ | |
| "bootcmd_net=run bootargs_base bootargs_nfs; " \ | |
| "tftpboot ${loadaddr} ${kernel}; bootm\0" \ | |
| "prg_uboot=tftpboot ${loadaddr} ${uboot}; " \ | |
| "protect off ${uboot_addr} 0xa003ffff; " \ | |
| "erase ${uboot_addr} 0xa003ffff; " \ | |
| "cp.b ${loadaddr} ${uboot_addr} ${filesize}; " \ | |
| "setenv filesize; saveenv\0" | |
| #define CONFIG_CS8900 | |
| #define CONFIG_CS8900_BASE 0xb4020300 | |
| #define CONFIG_CS8900_BUS16 1 /* follow the Linux driver */ | |
| /* | |
| * The MX31ADS board seems to have a hardware "peculiarity" confirmed under | |
| * U-Boot, RedBoot and Linux: the ethernet Rx signal is reaching the CS8900A | |
| * controller inverted. The controller is capable of detecting and correcting | |
| * this, but it needs 4 network packets for that. Which means, at startup, you | |
| * will not receive answers to the first 4 packest, unless there have been some | |
| * broadcasts on the network, or your board is on a hub. Reducing the ARP | |
| * timeout from default 5 seconds to 200ms we speed up the initial TFTP | |
| * transfer, should the user wish one, significantly. | |
| */ | |
| #define CONFIG_ARP_TIMEOUT 200UL | |
| /* | |
| * Miscellaneous configurable options | |
| */ | |
| #define CONFIG_SYS_LONGHELP /* undef to save memory */ | |
| #define CONFIG_SYS_PROMPT "=> " | |
| #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ | |
| /* Print Buffer Size */ | |
| #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) | |
| #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
| #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
| #define CONFIG_SYS_MEMTEST_START 0 /* memtest works on */ | |
| #define CONFIG_SYS_MEMTEST_END 0x10000 | |
| #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR | |
| #define CONFIG_SYS_HZ 1000 | |
| #define CONFIG_CMDLINE_EDITING 1 | |
| /*----------------------------------------------------------------------- | |
| * Physical Memory Map | |
| */ | |
| #define CONFIG_NR_DRAM_BANKS 1 | |
| #define PHYS_SDRAM_1 CSD0_BASE | |
| #define PHYS_SDRAM_1_SIZE (128 * 1024 * 1024) | |
| #define CONFIG_BOARD_EARLY_INIT_F | |
| #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 | |
| #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR | |
| #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE | |
| #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ | |
| GENERATED_GBL_DATA_SIZE) | |
| #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ | |
| CONFIG_SYS_GBL_DATA_OFFSET) | |
| /*----------------------------------------------------------------------- | |
| * FLASH and environment organization | |
| */ | |
| #define CONFIG_SYS_FLASH_BASE CS0_BASE | |
| #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ | |
| #define CONFIG_SYS_MAX_FLASH_SECT 262 /* max number of sectors on one chip */ | |
| #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE /* Monitor at beginning of flash */ | |
| #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256KiB */ | |
| #define CONFIG_ENV_IS_IN_FLASH 1 | |
| #define CONFIG_ENV_SECT_SIZE (128 * 1024) | |
| #define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE | |
| #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) | |
| /* Address and size of Redundant Environment Sector */ | |
| #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SIZE) | |
| #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE | |
| /*----------------------------------------------------------------------- | |
| * CFI FLASH driver setup | |
| */ | |
| #define CONFIG_SYS_FLASH_CFI 1 /* Flash memory is CFI compliant */ | |
| #define CONFIG_FLASH_CFI_DRIVER 1 /* Use drivers/cfi_flash.c */ | |
| #define CONFIG_FLASH_SPANSION_S29WS_N 1 /* A non-standard buffered write algorithm */ | |
| #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* Use buffered writes (~10x faster) */ | |
| #define CONFIG_SYS_FLASH_PROTECTION 1 /* Use hardware sector protection */ | |
| /* | |
| * JFFS2 partitions | |
| */ | |
| #undef CONFIG_CMD_MTDPARTS | |
| #define CONFIG_JFFS2_DEV "nor0" | |
| #endif /* __CONFIG_H */ |