| // SPDX-License-Identifier: GPL-2.0 | |
| // | |
| // Copyright 2019 NXP | |
| /dts-v1/; | |
| #include "imx7ulp.dtsi" | |
| #include <dt-bindings/input/input.h> | |
| / { | |
| model = "Embedded Artists i.MX7ULP COM"; | |
| compatible = "ea,imx7ulp-com", "fsl,imx7ulp"; | |
| chosen { | |
| stdout-path = &lpuart4; | |
| }; | |
| memory@60000000 { | |
| device_type = "memory"; | |
| reg = <0x60000000 0x4000000>; | |
| }; | |
| }; | |
| &lpuart4 { | |
| pinctrl-names = "default"; | |
| pinctrl-0 = <&pinctrl_lpuart4>; | |
| status = "okay"; | |
| }; | |
| &usbotg1 { | |
| pinctrl-names = "default"; | |
| pinctrl-0 = <&pinctrl_usbotg1_id>; | |
| srp-disable; | |
| hnp-disable; | |
| adp-disable; | |
| status = "okay"; | |
| }; | |
| &usdhc0 { | |
| assigned-clocks = <&pcc2 IMX7ULP_CLK_USDHC0>; | |
| assigned-clock-parents = <&scg1 IMX7ULP_CLK_APLL_PFD1>; | |
| pinctrl-names = "default"; | |
| pinctrl-0 = <&pinctrl_usdhc0>; | |
| non-removable; | |
| bus-width = <8>; | |
| no-1-8-v; | |
| status = "okay"; | |
| }; | |
| &iomuxc1 { | |
| pinctrl_lpuart4: lpuart4grp { | |
| fsl,pins = < | |
| IMX7ULP_PAD_PTC3__LPUART4_RX 0x3 | |
| IMX7ULP_PAD_PTC2__LPUART4_TX 0x3 | |
| >; | |
| }; | |
| pinctrl_usbotg1_id: otg1idgrp { | |
| fsl,pins = < | |
| IMX7ULP_PAD_PTC13__USB0_ID 0x10003 | |
| >; | |
| }; | |
| pinctrl_usdhc0: usdhc0grp { | |
| fsl,pins = < | |
| IMX7ULP_PAD_PTD1__SDHC0_CMD 0x43 | |
| IMX7ULP_PAD_PTD2__SDHC0_CLK 0x10042 | |
| IMX7ULP_PAD_PTD3__SDHC0_D7 0x43 | |
| IMX7ULP_PAD_PTD4__SDHC0_D6 0x43 | |
| IMX7ULP_PAD_PTD5__SDHC0_D5 0x43 | |
| IMX7ULP_PAD_PTD6__SDHC0_D4 0x43 | |
| IMX7ULP_PAD_PTD7__SDHC0_D3 0x43 | |
| IMX7ULP_PAD_PTD8__SDHC0_D2 0x43 | |
| IMX7ULP_PAD_PTD9__SDHC0_D1 0x43 | |
| IMX7ULP_PAD_PTD10__SDHC0_D0 0x43 | |
| IMX7ULP_PAD_PTD11__SDHC0_DQS 0x42 | |
| >; | |
| }; | |
| }; |