| // SPDX-License-Identifier: GPL-2.0 | |
| /dts-v1/; | |
| #include <dt-bindings/input/input.h> | |
| #include "tegra30.dtsi" | |
| / { | |
| model = "Microsoft Surface RT Tablet"; | |
| compatible = "microsoft,surface-rt", "nvidia,tegra30"; | |
| chosen { | |
| stdout-path = &uarta; | |
| }; | |
| aliases { | |
| i2c0 = &pwr_i2c; | |
| mmc0 = &sdmmc4; /* eMMC */ | |
| mmc1 = &sdmmc1; /* uSD slot */ | |
| rtc0 = &pmic; | |
| rtc1 = "/rtc@7000e000"; | |
| spi0 = &spi4; | |
| usb0 = &usb1; | |
| }; | |
| memory { | |
| device_type = "memory"; | |
| reg = <0x80000000 0x80000000>; | |
| }; | |
| host1x@50000000 { | |
| dc@54200000 { | |
| rgb { | |
| status = "okay"; | |
| nvidia,panel = <&panel>; | |
| }; | |
| }; | |
| }; | |
| gpio@6000d000 { | |
| /* in case usb vbus is on for some reason */ | |
| usb-vbus-hog { | |
| gpio-hog; | |
| gpios = <TEGRA_GPIO(DD, 6) GPIO_ACTIVE_HIGH>; | |
| output-low; | |
| }; | |
| }; | |
| pinmux@70000868 { | |
| pinctrl-names = "default"; | |
| pinctrl-0 = <&state_default>; | |
| state_default: pinmux { | |
| /* SDMMC1 pinmux */ | |
| sdmmc1-clk { | |
| nvidia,pins = "sdmmc1_clk_pz0"; | |
| nvidia,function = "sdmmc1"; | |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| }; | |
| sdmmc1-cmd { | |
| nvidia,pins = "sdmmc1_dat3_py4", | |
| "sdmmc1_dat2_py5", | |
| "sdmmc1_dat1_py6", | |
| "sdmmc1_dat0_py7", | |
| "sdmmc1_cmd_pz1"; | |
| nvidia,function = "sdmmc1"; | |
| nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
| nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| }; | |
| /* SDMMC3 pinmux */ | |
| sdmmc3-clk { | |
| nvidia,pins = "sdmmc3_clk_pa6"; | |
| nvidia,function = "sdmmc3"; | |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| }; | |
| sdmmc3-cmd { | |
| nvidia,pins = "sdmmc3_cmd_pa7", | |
| "sdmmc3_dat3_pb4", | |
| "sdmmc3_dat2_pb5", | |
| "sdmmc3_dat1_pb6", | |
| "sdmmc3_dat0_pb7", | |
| "sdmmc3_dat5_pd0"; | |
| nvidia,function = "sdmmc3"; | |
| nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
| nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| }; | |
| /* SDMMC4 pinmux */ | |
| sdmmc4-clk { | |
| nvidia,pins = "sdmmc4_clk_pcc4"; | |
| nvidia,function = "sdmmc4"; | |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| nvidia,lock = <TEGRA_PIN_DISABLE>; | |
| nvidia,io-reset = <TEGRA_PIN_DISABLE>; | |
| }; | |
| sdmmc4-cmd { | |
| nvidia,pins = "sdmmc4_cmd_pt7", | |
| "sdmmc4_dat0_paa0", | |
| "sdmmc4_dat1_paa1", | |
| "sdmmc4_dat2_paa2", | |
| "sdmmc4_dat3_paa3", | |
| "sdmmc4_dat4_paa4", | |
| "sdmmc4_dat5_paa5", | |
| "sdmmc4_dat6_paa6", | |
| "sdmmc4_dat7_paa7", | |
| "sdmmc4_rst_n_pcc3"; | |
| nvidia,function = "sdmmc4"; | |
| nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
| nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| nvidia,lock = <TEGRA_PIN_DISABLE>; | |
| nvidia,io-reset = <TEGRA_PIN_DISABLE>; | |
| }; | |
| cam-mclk { | |
| nvidia,pins = "cam_mclk_pcc0"; | |
| nvidia,function = "vi_alt3"; | |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| }; | |
| /* I2C pinmux */ | |
| gen1-i2c { | |
| nvidia,pins = "gen1_i2c_scl_pc4", | |
| "gen1_i2c_sda_pc5"; | |
| nvidia,function = "i2c1"; | |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| nvidia,open-drain = <TEGRA_PIN_ENABLE>; | |
| nvidia,lock = <TEGRA_PIN_DISABLE>; | |
| }; | |
| gen2-i2c { | |
| nvidia,pins = "gen2_i2c_scl_pt5", | |
| "gen2_i2c_sda_pt6"; | |
| nvidia,function = "i2c2"; | |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| nvidia,open-drain = <TEGRA_PIN_ENABLE>; | |
| nvidia,lock = <TEGRA_PIN_DISABLE>; | |
| }; | |
| cam-i2c { | |
| nvidia,pins = "cam_i2c_scl_pbb1", | |
| "cam_i2c_sda_pbb2"; | |
| nvidia,function = "i2c3"; | |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| nvidia,open-drain = <TEGRA_PIN_ENABLE>; | |
| nvidia,lock = <TEGRA_PIN_DISABLE>; | |
| }; | |
| ddc-i2c { | |
| nvidia,pins = "ddc_scl_pv4", | |
| "ddc_sda_pv5"; | |
| nvidia,function = "i2c4"; | |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| nvidia,lock = <TEGRA_PIN_DISABLE>; | |
| }; | |
| pwr-i2c { | |
| nvidia,pins = "pwr_i2c_scl_pz6", | |
| "pwr_i2c_sda_pz7"; | |
| nvidia,function = "i2cpwr"; | |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| nvidia,open-drain = <TEGRA_PIN_ENABLE>; | |
| nvidia,lock = <TEGRA_PIN_DISABLE>; | |
| }; | |
| /* HDMI pinmux */ | |
| hdmi-cec { | |
| nvidia,pins = "hdmi_cec_pee3"; | |
| nvidia,function = "cec"; | |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| }; | |
| hdmi-hpd { | |
| nvidia,pins = "hdmi_int_pn7"; | |
| nvidia,function = "hdmi"; | |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| }; | |
| /* UART-A */ | |
| ulpi-data0-po1 { | |
| nvidia,pins = "ulpi_data0_po1"; | |
| nvidia,function = "uarta"; | |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| }; | |
| ulpi-data1-po2 { | |
| nvidia,pins = "ulpi_data1_po2"; | |
| nvidia,function = "uarta"; | |
| nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| }; | |
| ulpi-data2-po3 { | |
| nvidia,pins = "ulpi_data2_po3", | |
| "ulpi_data3_po4"; | |
| nvidia,function = "uarta"; | |
| nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
| nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| }; | |
| /* UART-B */ | |
| uartb-txd-rxd { | |
| nvidia,pins = "uart2_txd_pc2", | |
| "uart2_rxd_pc3"; | |
| nvidia,function = "uartb"; | |
| nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| }; | |
| uartb-cts-rts { | |
| nvidia,pins = "uart2_cts_n_pj5", | |
| "uart2_rts_n_pj6"; | |
| nvidia,function = "gmi"; | |
| nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| }; | |
| /* UART-C */ | |
| uartc-rxd-cts { | |
| nvidia,pins = "uart3_cts_n_pa1", | |
| "uart3_rxd_pw7"; | |
| nvidia,function = "uartc"; | |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| }; | |
| uartc-txd-rts { | |
| nvidia,pins = "uart3_rts_n_pc0", | |
| "uart3_txd_pw6"; | |
| nvidia,function = "uartc"; | |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| }; | |
| /* I2S pinmux */ | |
| dap-i2s0-out { | |
| nvidia,pins = "dap1_fs_pn0", | |
| "dap1_sclk_pn3"; | |
| nvidia,function = "i2s0"; | |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| }; | |
| dap-i2s0-in { | |
| nvidia,pins = "dap1_din_pn1", | |
| "dap1_dout_pn2"; | |
| nvidia,function = "i2s0"; | |
| nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| }; | |
| dap-i2s1 { | |
| nvidia,pins = "dap2_fs_pa2", | |
| "dap2_sclk_pa3", | |
| "dap2_din_pa4", | |
| "dap2_dout_pa5"; | |
| nvidia,function = "i2s1"; | |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| }; | |
| dap-i2s2 { | |
| nvidia,pins = "dap3_fs_pp0", | |
| "dap3_din_pp1", | |
| "dap3_dout_pp2", | |
| "dap3_sclk_pp3"; | |
| nvidia,function = "i2s2"; | |
| nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| }; | |
| dap-i2s3 { | |
| nvidia,pins = "dap4_fs_pp4", | |
| "dap4_din_pp5", | |
| "dap4_dout_pp6", | |
| "dap4_sclk_pp7"; | |
| nvidia,function = "i2s3"; | |
| nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| }; | |
| pbb0 { | |
| nvidia,pins = "pbb0", "pbb7"; | |
| nvidia,function = "i2s4"; | |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| }; | |
| pcc1 { | |
| nvidia,pins = "pcc1"; | |
| nvidia,function = "i2s4"; | |
| nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| }; | |
| pcc2 { | |
| nvidia,pins = "pcc2"; | |
| nvidia,function = "i2s4"; | |
| nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
| nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| }; | |
| /* PCI-e pinmux */ | |
| pex-l2-rst-n { | |
| nvidia,pins = "pex_l2_rst_n_pcc6", | |
| "pex_wake_n_pdd3", | |
| "pex_l1_rst_n_pdd5"; | |
| nvidia,function = "pcie"; | |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| }; | |
| pex-l2-clkreq-n { | |
| nvidia,pins = "pex_l2_clkreq_n_pcc7", | |
| "pex_l0_prsnt_n_pdd0", | |
| "pex_l0_rst_n_pdd1", | |
| "pex_l0_clkreq_n_pdd2", | |
| "pex_l1_prsnt_n_pdd4", | |
| "pex_l1_clkreq_n_pdd6", | |
| "pex_l2_prsnt_n_pdd7"; | |
| nvidia,function = "pcie"; | |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| }; | |
| /* SPI pinmux */ | |
| spi1-miso { | |
| nvidia,pins = "spi1_miso_px7"; | |
| nvidia,function = "spi1"; | |
| nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| }; | |
| ulpi-clk { | |
| nvidia,pins = "ulpi_clk_py0", | |
| "ulpi_dir_py1", | |
| "ulpi_nxt_py2", | |
| "ulpi_stp_py3"; | |
| nvidia,function = "spi1"; | |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| }; | |
| ulpi-data7 { | |
| nvidia,pins = "ulpi_data7_po0", | |
| "ulpi_data4_po5", | |
| "ulpi_data5_po6", | |
| "ulpi_data6_po7", | |
| "spi1_mosi_px4", | |
| "spi1_sck_px5", | |
| "spi1_cs0_n_px6"; | |
| nvidia,function = "spi2"; | |
| nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| }; | |
| spi2-cs1-n { | |
| nvidia,pins = "spi2_cs1_n_pw2"; | |
| nvidia,function = "spi3"; | |
| nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
| nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| }; | |
| spi2-cs2-n { | |
| nvidia,pins = "spi2_cs2_n_pw3"; | |
| nvidia,function = "spi3"; | |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| }; | |
| gmi-a17 { | |
| nvidia,pins = "gmi_a17_pb0", | |
| "gmi_a18_pb1", | |
| "gmi_a16_pj7", | |
| "gmi_a19_pk7"; | |
| nvidia,function = "spi4"; | |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| }; | |
| spi2-sck { | |
| nvidia,pins = "spi2_sck_px2"; | |
| nvidia,function = "spi6"; | |
| nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
| nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| }; | |
| /* Display A pinmux */ | |
| lcd-pclk { | |
| nvidia,pins = "lcd_pclk_pb3", | |
| "lcd_dc1_pd2", | |
| "lcd_d0_pe0", | |
| "lcd_d1_pe1", | |
| "lcd_d2_pe2", | |
| "lcd_d3_pe3", | |
| "lcd_d4_pe4", | |
| "lcd_d5_pe5", | |
| "lcd_d6_pe6", | |
| "lcd_d7_pe7", | |
| "lcd_d8_pf0", | |
| "lcd_d9_pf1", | |
| "lcd_d10_pf2", | |
| "lcd_d11_pf3", | |
| "lcd_d12_pf4", | |
| "lcd_d13_pf5", | |
| "lcd_d14_pf6", | |
| "lcd_d15_pf7", | |
| "lcd_de_pj1", | |
| "lcd_d16_pm0", | |
| "lcd_d17_pm1", | |
| "lcd_d18_pm2", | |
| "lcd_d19_pm3", | |
| "lcd_d20_pm4", | |
| "lcd_d21_pm5", | |
| "lcd_d22_pm6", | |
| "lcd_d23_pm7", | |
| "lcd_sdout_pn5", | |
| "lcd_dc0_pn6", | |
| "lcd_m1_pw1", | |
| "lcd_sdin_pz2", | |
| "lcd_sck_pz4"; | |
| nvidia,function = "displaya"; | |
| nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
| nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| }; | |
| lcd-pwr1 { | |
| nvidia,pins = "lcd_pwr1_pc1", | |
| "lcd_pwr2_pc6"; | |
| nvidia,function = "displaya"; | |
| nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| }; | |
| lcd-hsync { | |
| nvidia,pins = "lcd_hsync_pj3", | |
| "lcd_vsync_pj4", | |
| "lcd_cs0_n_pn4", | |
| "lcd_cs1_n_pw0", | |
| "lcd_wr_n_pz3"; | |
| nvidia,function = "displaya"; | |
| nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
| nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| }; | |
| lcd-pwr0 { | |
| nvidia,pins = "lcd_pwr0_pb2"; | |
| nvidia,function = "displaya"; | |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| }; | |
| crt-hsync-pv6 { | |
| nvidia,pins = "crt_hsync_pv6", | |
| "crt_vsync_pv7"; | |
| nvidia,function = "crt"; | |
| nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| }; | |
| blink { | |
| nvidia,pins = "clk_32k_out_pa0"; | |
| nvidia,function = "blink"; | |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| }; | |
| /* KBC keys */ | |
| kb-col0 { | |
| nvidia,pins = "kb_col0_pq0", | |
| "kb_col1_pq1", | |
| "kb_col2_pq2", | |
| "kb_col3_pq3", | |
| "kb_col4_pq4", | |
| "kb_col5_pq5", | |
| "kb_col6_pq6", | |
| "kb_col7_pq7", | |
| "kb_row12_ps4"; | |
| nvidia,function = "kbc"; | |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| }; | |
| kb-row0 { | |
| nvidia,pins = "kb_row0_pr0", | |
| "kb_row1_pr1", | |
| "kb_row5_pr5"; | |
| nvidia,function = "kbc"; | |
| nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
| nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| }; | |
| kb-row2 { | |
| nvidia,pins = "kb_row2_pr2", | |
| "kb_row3_pr3", | |
| "kb_row6_pr6", | |
| "kb_row7_pr7", | |
| "kb_row11_ps3"; | |
| nvidia,function = "kbc"; | |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| }; | |
| kb-row4 { | |
| nvidia,pins = "kb_row4_pr4", | |
| "kb_row9_ps1"; | |
| nvidia,function = "kbc"; | |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| }; | |
| kb-row8 { | |
| nvidia,pins = "kb_row8_ps0", | |
| "kb_row10_ps2"; | |
| nvidia,function = "kbc"; | |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| }; | |
| kb-row13 { | |
| nvidia,pins = "kb_row13_ps5", | |
| "kb_row14_ps6", | |
| "kb_row15_ps7"; | |
| nvidia,function = "kbc"; | |
| nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
| nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| }; | |
| /* SPDIF pinmux */ | |
| spdif-pins { | |
| nvidia,pins = "spdif_out_pk5", | |
| "spdif_in_pk6"; | |
| nvidia,function = "spdif"; | |
| nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| }; | |
| sdmmc3-dat6 { | |
| nvidia,pins = "sdmmc3_dat6_pd3", | |
| "sdmmc3_dat7_pd4"; | |
| nvidia,function = "spdif"; | |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| }; | |
| jtag-rtck { | |
| nvidia,pins = "jtag_rtck_pu7"; | |
| nvidia,function = "rtck"; | |
| nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
| nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| }; | |
| /* GMI pinmux */ | |
| gmi-wp-n { | |
| nvidia,pins = "gmi_wp_n_pc7", | |
| "gmi_cs7_n_pi6"; | |
| nvidia,function = "gmi"; | |
| nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| }; | |
| sdmmc3-dat4 { | |
| nvidia,pins = "sdmmc3_dat4_pd1", | |
| "gmi_ad9_ph1"; | |
| nvidia,function = "pwm1"; | |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| }; | |
| gmi-ad0-pg0 { | |
| nvidia,pins = "gmi_ad0_pg0", | |
| "gmi_ad1_pg1", | |
| "gmi_ad2_pg2", | |
| "gmi_ad3_pg3", | |
| "gmi_ad4_pg4", | |
| "gmi_ad5_pg5", | |
| "gmi_ad6_pg6", | |
| "gmi_ad7_pg7", | |
| "gmi_ad15_ph7"; | |
| nvidia,function = "gmi"; | |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| }; | |
| gmi-ad8 { | |
| nvidia,pins = "gmi_ad8_ph0"; | |
| nvidia,function = "pwm0"; | |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| }; | |
| gmi-ad10 { | |
| nvidia,pins = "gmi_ad10_ph2", | |
| "gmi_ad11_ph3"; | |
| nvidia,function = "gmi"; | |
| nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| }; | |
| gmi-ad12 { | |
| nvidia,pins = "gmi_ad12_ph4", | |
| "gmi_ad13_ph5", | |
| "gmi_iordy_pi5", | |
| "gmi_cs0_n_pj0", | |
| "pu1", | |
| "pu2", | |
| "pv1", | |
| "pv2", | |
| "pv3"; | |
| nvidia,function = "rsvd1"; | |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| }; | |
| gmi-wr-n { | |
| nvidia,pins = "gmi_wr_n_pi0", | |
| "gmi_oe_n_pi1", | |
| "gmi_adv_n_pk0", | |
| "gmi_clk_pk1"; | |
| nvidia,function = "gmi"; | |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| }; | |
| gmi-dqs { | |
| nvidia,pins = "gmi_dqs_pi2"; | |
| nvidia,function = "rsvd1"; | |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| }; | |
| gmi-wait { | |
| nvidia,pins = "gmi_wait_pi7", | |
| "gmi_cs2_n_pk3", | |
| "gmi_cs3_n_pk4"; | |
| nvidia,function = "gmi"; | |
| nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
| nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| }; | |
| gmi-cs4-n { | |
| nvidia,pins = "gmi_cs4_n_pk2"; | |
| nvidia,function = "rsvd1"; | |
| nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| }; | |
| gmi-ad14-ph6 { | |
| nvidia,pins = "gmi_ad14_ph6"; | |
| nvidia,function = "rsvd1"; | |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| }; | |
| /* VI pinmux */ | |
| vi-d1-pd5 { | |
| nvidia,pins = "vi_d1_pd5", | |
| "vi_vsync_pd6", | |
| "vi_d2_pl0", | |
| "vi_d4_pl2", | |
| "vi_d5_pl3", | |
| "vi_d6_pl4", | |
| "vi_pclk_pt0", | |
| "vi_d10_pt2", | |
| "vi_d0_pt4"; | |
| nvidia,function = "rsvd1"; | |
| nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| nvidia,lock = <TEGRA_PIN_DISABLE>; | |
| nvidia,io-reset = <TEGRA_PIN_DISABLE>; | |
| }; | |
| vi-d3-pl1 { | |
| nvidia,pins = "vi_d3_pl1"; | |
| nvidia,function = "rsvd1"; | |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| nvidia,lock = <TEGRA_PIN_DISABLE>; | |
| nvidia,io-reset = <TEGRA_PIN_DISABLE>; | |
| }; | |
| vi-hsync-pd7 { | |
| nvidia,pins = "vi_hsync_pd7", | |
| "vi_d7_pl5", | |
| "vi_d8_pl6", | |
| "vi_d9_pl7"; | |
| nvidia,function = "rsvd1"; | |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| nvidia,lock = <TEGRA_PIN_DISABLE>; | |
| nvidia,io-reset = <TEGRA_PIN_DISABLE>; | |
| }; | |
| vi-mclk-pt1 { | |
| nvidia,pins = "vi_mclk_pt1"; | |
| nvidia,function = "vi"; | |
| nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| nvidia,lock = <TEGRA_PIN_DISABLE>; | |
| nvidia,io-reset = <TEGRA_PIN_DISABLE>; | |
| }; | |
| vi-d11-pt3 { | |
| nvidia,pins = "vi_d11_pt3"; | |
| nvidia,function = "ddr"; | |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| nvidia,lock = <TEGRA_PIN_DISABLE>; | |
| nvidia,io-reset = <TEGRA_PIN_DISABLE>; | |
| }; | |
| /* PORT U */ | |
| pu0 { | |
| nvidia,pins = "pu0"; | |
| nvidia,function = "owr"; | |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| }; | |
| pu3 { | |
| nvidia,pins = "pu3"; | |
| nvidia,function = "pwm0"; | |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| }; | |
| pu4 { | |
| nvidia,pins = "pu4"; | |
| nvidia,function = "pwm1"; | |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| }; | |
| pu5 { | |
| nvidia,pins = "pu5"; | |
| nvidia,function = "pwm2"; | |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| }; | |
| pu6 { | |
| nvidia,pins = "pu6"; | |
| nvidia,function = "pwm3"; | |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| }; | |
| /* PORT V */ | |
| pv0 { | |
| nvidia,pins = "pv0"; | |
| nvidia,function = "rsvd1"; | |
| nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
| nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| }; | |
| /* PORT BB */ | |
| pbb3 { | |
| nvidia,pins = "pbb3"; | |
| nvidia,function = "vgp3"; | |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| }; | |
| pbb4 { | |
| nvidia,pins = "pbb4"; | |
| nvidia,function = "vgp4"; | |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| }; | |
| pbb5 { | |
| nvidia,pins = "pbb5"; | |
| nvidia,function = "vgp5"; | |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| }; | |
| pbb6 { | |
| nvidia,pins = "pbb6"; | |
| nvidia,function = "vgp6"; | |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| }; | |
| /* CLK pinmux */ | |
| clk1-out-pw4 { | |
| nvidia,pins = "clk1_out_pw4"; | |
| nvidia,function = "extperiph1"; | |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| }; | |
| clk2-out-pw5 { | |
| nvidia,pins = "clk2_out_pw5"; | |
| nvidia,function = "extperiph2"; | |
| nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| }; | |
| clk2-req-pcc5 { | |
| nvidia,pins = "clk2_req_pcc5", | |
| "clk1_req_pee2"; | |
| nvidia,function = "dap"; | |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| }; | |
| clk3-out-pee0 { | |
| nvidia,pins = "clk3_out_pee0"; | |
| nvidia,function = "extperiph3"; | |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| }; | |
| clk3-req-pee1 { | |
| nvidia,pins = "clk3_req_pee1"; | |
| nvidia,function = "dev3"; | |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| }; | |
| sys-clk-req-pz5 { | |
| nvidia,pins = "sys_clk_req_pz5"; | |
| nvidia,function = "sysclk"; | |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| }; | |
| owr { | |
| nvidia,pins = "owr"; | |
| nvidia,function = "owr"; | |
| nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
| nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| }; | |
| /* GPIO power/drive control */ | |
| drive-sdio1 { | |
| nvidia,pins = "drive_sdio1", | |
| "drive_sdio3"; | |
| nvidia,high-speed-mode = <TEGRA_PIN_DISABLE>; | |
| nvidia,schmitt = <TEGRA_PIN_DISABLE>; | |
| nvidia,pull-down-strength = <46>; | |
| nvidia,pull-up-strength = <42>; | |
| nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FAST>; | |
| nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FAST>; | |
| }; | |
| }; | |
| }; | |
| uarta: serial@70006000 { | |
| status = "okay"; | |
| }; | |
| pwm: pwm@7000a000 { | |
| status = "okay"; | |
| }; | |
| pwr_i2c: i2c@7000d000 { | |
| status = "okay"; | |
| clock-frequency = <400000>; | |
| /* Texas Instruments TPS659110 PMIC */ | |
| pmic: tps65911@2d { | |
| compatible = "ti,tps65911"; | |
| reg = <0x2d>; | |
| interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; | |
| #interrupt-cells = <2>; | |
| interrupt-controller; | |
| ti,system-power-controller; | |
| #gpio-cells = <2>; | |
| gpio-controller; | |
| regulators { | |
| vdd_1v8_vio: vddio { | |
| regulator-name = "vdd_1v8_gen"; | |
| regulator-min-microvolt = <1800000>; | |
| regulator-max-microvolt = <1800000>; | |
| regulator-always-on; | |
| regulator-boot-on; | |
| }; | |
| vddio_usd: ldo5 { | |
| regulator-name = "vddio_usd"; | |
| regulator-min-microvolt = <3300000>; | |
| regulator-max-microvolt = <3300000>; | |
| regulator-always-on; | |
| regulator-boot-on; | |
| }; | |
| }; | |
| }; | |
| }; | |
| spi4: spi@7000da00 { | |
| status = "okay"; | |
| spi-max-frequency = <25000000>; | |
| spi-flash@1 { | |
| compatible = "winbond,w25q32", "jedec,spi-nor"; | |
| reg = <1>; | |
| spi-max-frequency = <20000000>; | |
| }; | |
| }; | |
| sdmmc1: mmc@78000000 { | |
| status = "okay"; | |
| bus-width = <4>; | |
| cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>; | |
| vmmc-supply = <&vdd_usd>; | |
| vqmmc-supply = <&vddio_usd>; | |
| }; | |
| sdmmc4: mmc@78000600 { | |
| status = "okay"; | |
| bus-width = <8>; | |
| non-removable; | |
| vmmc-supply = <&vdd_3v3_sys>; | |
| vqmmc-supply = <&vdd_1v8_vio>; | |
| }; | |
| /* Main USB port */ | |
| usb1: usb@7d000000 { | |
| status = "okay"; | |
| dr_mode = "otg"; | |
| nvidia,vbus-gpio = <&gpio TEGRA_GPIO(DD, 6) GPIO_ACTIVE_HIGH>; | |
| }; | |
| backlight: backlight { | |
| compatible = "pwm-backlight"; | |
| enable-gpios = <&gpio TEGRA_GPIO(DD, 0) GPIO_ACTIVE_HIGH>; | |
| pwms = <&pwm 0 50000>; | |
| brightness-levels = <1 35 70 105 140 175 210 255>; | |
| default-brightness-level = <5>; | |
| }; | |
| /* PMIC has a built-in 32KHz oscillator which is used by PMC */ | |
| clk32k_in: clock-32k { | |
| compatible = "fixed-clock"; | |
| #clock-cells = <0>; | |
| clock-frequency = <32768>; | |
| clock-output-names = "pmic-oscillator"; | |
| }; | |
| extcon-keys { | |
| compatible = "gpio-keys"; | |
| switch-hall-sensor { | |
| label = "Hall Sensor"; | |
| gpios = <&gpio TEGRA_GPIO(L, 1) GPIO_ACTIVE_HIGH>; | |
| linux,code = <SW_LID>; | |
| }; | |
| }; | |
| gpio-keys { | |
| compatible = "gpio-keys"; | |
| key-power { | |
| label = "Power"; | |
| gpios = <&gpio TEGRA_GPIO(V, 0) GPIO_ACTIVE_HIGH>; | |
| linux,code = <KEY_CANCEL>; | |
| }; | |
| key-volume-down { | |
| label = "Volume Down"; | |
| gpios = <&gpio TEGRA_GPIO(S, 6) GPIO_ACTIVE_LOW>; | |
| linux,code = <KEY_DOWN>; | |
| }; | |
| key-volume-up { | |
| label = "Volume Up"; | |
| gpios = <&gpio TEGRA_GPIO(S, 7) GPIO_ACTIVE_LOW>; | |
| linux,code = <KEY_UP>; | |
| }; | |
| key-windows-button { | |
| label = "Windows Button"; | |
| gpios = <&gpio TEGRA_GPIO(S, 5) GPIO_ACTIVE_HIGH>; | |
| linux,code = <KEY_ENTER>; | |
| }; | |
| }; | |
| panel: panel { | |
| compatible = "simple-panel"; | |
| power-supply = <&vdd_pnl_reg>; | |
| enable-gpios = <&gpio TEGRA_GPIO(B, 2) GPIO_ACTIVE_HIGH>; | |
| backlight = <&backlight>; | |
| display-timings { | |
| timing@0 { | |
| /* 1366x768@60Hz */ | |
| clock-frequency = <71980000>; | |
| hactive = <1366>; | |
| hfront-porch = <56>; | |
| hback-porch = <106>; | |
| hsync-len = <14>; | |
| vactive = <768>; | |
| vfront-porch = <3>; | |
| vback-porch = <6>; | |
| vsync-len = <1>; | |
| }; | |
| }; | |
| }; | |
| vdd_3v3_sys: regulator-3v { | |
| compatible = "regulator-fixed"; | |
| regulator-name = "vdd_3v3_sys"; | |
| regulator-min-microvolt = <3300000>; | |
| regulator-max-microvolt = <3300000>; | |
| regulator-always-on; | |
| regulator-boot-on; | |
| }; | |
| vdd_usd: regulator-usd { | |
| compatible = "regulator-fixed"; | |
| regulator-name = "vdd_usd"; | |
| regulator-min-microvolt = <3300000>; | |
| regulator-max-microvolt = <3300000>; | |
| gpio = <&gpio TEGRA_GPIO(D, 7) GPIO_ACTIVE_HIGH>; | |
| enable-active-high; | |
| }; | |
| vdd_pnl_reg: regulator-pnl { | |
| compatible = "regulator-fixed"; | |
| regulator-name = "vdd_panel"; | |
| regulator-min-microvolt = <3300000>; | |
| regulator-max-microvolt = <3300000>; | |
| gpio = <&gpio TEGRA_GPIO(DD, 2) GPIO_ACTIVE_HIGH>; | |
| enable-active-high; | |
| }; | |
| }; |