| // SPDX-License-Identifier: GPL-2.0 | |
| /dts-v1/; | |
| #include <dt-bindings/input/input.h> | |
| #include "tegra30.dtsi" | |
| / { | |
| model = "Ouya Game Console"; | |
| compatible = "ouya,ouya", "nvidia,tegra30"; | |
| chosen { | |
| stdout-path = &uartd; | |
| }; | |
| aliases { | |
| i2c0 = &pwr_i2c; | |
| i2c1 = &hdmi_ddc; | |
| mmc0 = &sdmmc4; | |
| rtc0 = &pmic; | |
| rtc1 = "/rtc@7000e000"; | |
| usb0 = µ_usb; | |
| usb1 = ðernet_usb; | |
| usb2 = &fullsize_usb; | |
| }; | |
| memory { | |
| device_type = "memory"; | |
| reg = <0x80000000 0x40000000>; | |
| }; | |
| host1x@50000000 { | |
| dc@54200000 { | |
| status = "disabled"; | |
| }; | |
| hdmi: hdmi@54280000 { | |
| status = "okay"; | |
| hdmi-supply = <&sys_3v3_reg>; | |
| pll-supply = <&ldo7_reg>; | |
| vdd-supply = <&vdd_vid_reg>; | |
| nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>; | |
| nvidia,ddc-i2c-bus = <&hdmi_ddc>; | |
| }; | |
| }; | |
| gpio@6000d000 { | |
| fan-en-hog { | |
| gpio-hog; | |
| gpios = <TEGRA_GPIO(J, 2) GPIO_ACTIVE_HIGH>; | |
| output-high; | |
| }; | |
| }; | |
| bsev@6001b000 { | |
| status = "okay"; | |
| }; | |
| pinmux@70000868 { | |
| pinctrl-names = "default"; | |
| pinctrl-0 = <&state_default>; | |
| state_default: pinmux { | |
| clk_32k_out_pa0 { | |
| nvidia,pins = "clk_32k_out_pa0"; | |
| nvidia,function = "blink"; | |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| }; | |
| uart3_cts_n_pa1 { | |
| nvidia,pins = "uart3_cts_n_pa1"; | |
| nvidia,function = "uartc"; | |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| }; | |
| dap2_fs_pa2 { | |
| nvidia,pins = "dap2_fs_pa2"; | |
| nvidia,function = "i2s1"; | |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| }; | |
| dap2_sclk_pa3 { | |
| nvidia,pins = "dap2_sclk_pa3"; | |
| nvidia,function = "i2s1"; | |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| }; | |
| dap2_din_pa4 { | |
| nvidia,pins = "dap2_din_pa4"; | |
| nvidia,function = "i2s1"; | |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| }; | |
| dap2_dout_pa5 { | |
| nvidia,pins = "dap2_dout_pa5"; | |
| nvidia,function = "i2s1"; | |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| }; | |
| sdmmc3_clk_pa6 { | |
| nvidia,pins = "sdmmc3_clk_pa6"; | |
| nvidia,function = "sdmmc3"; | |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| }; | |
| sdmmc3_cmd_pa7 { | |
| nvidia,pins = "sdmmc3_cmd_pa7"; | |
| nvidia,function = "sdmmc3"; | |
| nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
| nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| }; | |
| gmi_a17_pb0 { | |
| nvidia,pins = "gmi_a17_pb0"; | |
| nvidia,function = "spi4"; | |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| }; | |
| gmi_a18_pb1 { | |
| nvidia,pins = "gmi_a18_pb1"; | |
| nvidia,function = "spi4"; | |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| }; | |
| lcd_pwr0_pb2 { | |
| nvidia,pins = "lcd_pwr0_pb2"; | |
| nvidia,function = "displaya"; | |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| }; | |
| lcd_pclk_pb3 { | |
| nvidia,pins = "lcd_pclk_pb3"; | |
| nvidia,function = "displaya"; | |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| }; | |
| sdmmc3_dat3_pb4 { | |
| nvidia,pins = "sdmmc3_dat3_pb4"; | |
| nvidia,function = "sdmmc3"; | |
| nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
| nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| }; | |
| sdmmc3_dat2_pb5 { | |
| nvidia,pins = "sdmmc3_dat2_pb5"; | |
| nvidia,function = "sdmmc3"; | |
| nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
| nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| }; | |
| sdmmc3_dat1_pb6 { | |
| nvidia,pins = "sdmmc3_dat1_pb6"; | |
| nvidia,function = "sdmmc3"; | |
| nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
| nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| }; | |
| sdmmc3_dat0_pb7 { | |
| nvidia,pins = "sdmmc3_dat0_pb7"; | |
| nvidia,function = "sdmmc3"; | |
| nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
| nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| }; | |
| uart3_rts_n_pc0 { | |
| nvidia,pins = "uart3_rts_n_pc0"; | |
| nvidia,function = "uartc"; | |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| }; | |
| lcd_pwr1_pc1 { | |
| nvidia,pins = "lcd_pwr1_pc1"; | |
| nvidia,function = "displaya"; | |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| }; | |
| uart2_txd_pc2 { | |
| nvidia,pins = "uart2_txd_pc2"; | |
| nvidia,function = "uartb"; | |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| }; | |
| uart2_rxd_pc3 { | |
| nvidia,pins = "uart2_rxd_pc3"; | |
| nvidia,function = "uartb"; | |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| }; | |
| gen1_i2c_scl_pc4 { | |
| nvidia,pins = "gen1_i2c_scl_pc4"; | |
| nvidia,function = "i2c1"; | |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
| }; | |
| gen1_i2c_sda_pc5 { | |
| nvidia,pins = "gen1_i2c_sda_pc5"; | |
| nvidia,function = "i2c1"; | |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
| }; | |
| lcd_pwr2_pc6 { | |
| nvidia,pins = "lcd_pwr2_pc6"; | |
| nvidia,function = "displaya"; | |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| }; | |
| gmi_wp_n_pc7 { | |
| nvidia,pins = "gmi_wp_n_pc7"; | |
| nvidia,function = "gmi"; | |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| }; | |
| sdmmc3_dat5_pd0 { | |
| nvidia,pins = "sdmmc3_dat5_pd0"; | |
| nvidia,function = "sdmmc3"; | |
| nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
| nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| }; | |
| sdmmc3_dat4_pd1 { | |
| nvidia,pins = "sdmmc3_dat4_pd1"; | |
| nvidia,function = "sdmmc3"; | |
| nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
| nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| }; | |
| lcd_dc1_pd2 { | |
| nvidia,pins = "lcd_dc1_pd2"; | |
| nvidia,function = "displaya"; | |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| }; | |
| sdmmc3_dat6_pd3 { | |
| nvidia,pins = "sdmmc3_dat6_pd3"; | |
| nvidia,function = "spi4"; | |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| }; | |
| sdmmc3_dat7_pd4 { | |
| nvidia,pins = "sdmmc3_dat7_pd4"; | |
| nvidia,function = "spi4"; | |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| }; | |
| vi_d1_pd5 { | |
| nvidia,pins = "vi_d1_pd5"; | |
| nvidia,function = "sdmmc2"; | |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| }; | |
| vi_vsync_pd6 { | |
| nvidia,pins = "vi_vsync_pd6"; | |
| nvidia,function = "ddr"; | |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| }; | |
| vi_hsync_pd7 { | |
| nvidia,pins = "vi_hsync_pd7"; | |
| nvidia,function = "ddr"; | |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| }; | |
| lcd_d0_pe0 { | |
| nvidia,pins = "lcd_d0_pe0"; | |
| nvidia,function = "displaya"; | |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| }; | |
| lcd_d1_pe1 { | |
| nvidia,pins = "lcd_d1_pe1"; | |
| nvidia,function = "displaya"; | |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| }; | |
| lcd_d2_pe2 { | |
| nvidia,pins = "lcd_d2_pe2"; | |
| nvidia,function = "displaya"; | |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| }; | |
| lcd_d3_pe3 { | |
| nvidia,pins = "lcd_d3_pe3"; | |
| nvidia,function = "displaya"; | |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| }; | |
| lcd_d4_pe4 { | |
| nvidia,pins = "lcd_d4_pe4"; | |
| nvidia,function = "displaya"; | |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| }; | |
| lcd_d5_pe5 { | |
| nvidia,pins = "lcd_d5_pe5"; | |
| nvidia,function = "displaya"; | |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| }; | |
| lcd_d6_pe6 { | |
| nvidia,pins = "lcd_d6_pe6"; | |
| nvidia,function = "displaya"; | |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| }; | |
| lcd_d7_pe7 { | |
| nvidia,pins = "lcd_d7_pe7"; | |
| nvidia,function = "displaya"; | |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| }; | |
| lcd_d8_pf0 { | |
| nvidia,pins = "lcd_d8_pf0"; | |
| nvidia,function = "displaya"; | |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| }; | |
| lcd_d9_pf1 { | |
| nvidia,pins = "lcd_d9_pf1"; | |
| nvidia,function = "displaya"; | |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| }; | |
| lcd_d10_pf2 { | |
| nvidia,pins = "lcd_d10_pf2"; | |
| nvidia,function = "displaya"; | |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| }; | |
| lcd_d11_pf3 { | |
| nvidia,pins = "lcd_d11_pf3"; | |
| nvidia,function = "displaya"; | |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| }; | |
| lcd_d12_pf4 { | |
| nvidia,pins = "lcd_d12_pf4"; | |
| nvidia,function = "displaya"; | |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| }; | |
| lcd_d13_pf5 { | |
| nvidia,pins = "lcd_d13_pf5"; | |
| nvidia,function = "displaya"; | |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| }; | |
| lcd_d14_pf6 { | |
| nvidia,pins = "lcd_d14_pf6"; | |
| nvidia,function = "displaya"; | |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| }; | |
| lcd_d15_pf7 { | |
| nvidia,pins = "lcd_d15_pf7"; | |
| nvidia,function = "displaya"; | |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| }; | |
| gmi_ad0_pg0 { | |
| nvidia,pins = "gmi_ad0_pg0"; | |
| nvidia,function = "nand"; | |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| }; | |
| gmi_ad1_pg1 { | |
| nvidia,pins = "gmi_ad1_pg1"; | |
| nvidia,function = "nand"; | |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| }; | |
| gmi_ad2_pg2 { | |
| nvidia,pins = "gmi_ad2_pg2"; | |
| nvidia,function = "nand"; | |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| }; | |
| gmi_ad3_pg3 { | |
| nvidia,pins = "gmi_ad3_pg3"; | |
| nvidia,function = "nand"; | |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| }; | |
| gmi_ad4_pg4 { | |
| nvidia,pins = "gmi_ad4_pg4"; | |
| nvidia,function = "nand"; | |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| }; | |
| gmi_ad5_pg5 { | |
| nvidia,pins = "gmi_ad5_pg5"; | |
| nvidia,function = "nand"; | |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| }; | |
| gmi_ad6_pg6 { | |
| nvidia,pins = "gmi_ad6_pg6"; | |
| nvidia,function = "nand"; | |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| }; | |
| gmi_ad7_pg7 { | |
| nvidia,pins = "gmi_ad7_pg7"; | |
| nvidia,function = "nand"; | |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| }; | |
| gmi_ad8_ph0 { | |
| nvidia,pins = "gmi_ad8_ph0"; | |
| nvidia,function = "pwm0"; | |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| }; | |
| gmi_ad9_ph1 { | |
| nvidia,pins = "gmi_ad9_ph1"; | |
| nvidia,function = "pwm1"; | |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| }; | |
| gmi_ad10_ph2 { | |
| nvidia,pins = "gmi_ad10_ph2"; | |
| nvidia,function = "pwm2"; | |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| }; | |
| gmi_ad11_ph3 { | |
| nvidia,pins = "gmi_ad11_ph3"; | |
| nvidia,function = "nand"; | |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| }; | |
| gmi_ad12_ph4 { | |
| nvidia,pins = "gmi_ad12_ph4"; | |
| nvidia,function = "nand"; | |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| }; | |
| gmi_ad13_ph5 { | |
| nvidia,pins = "gmi_ad13_ph5"; | |
| nvidia,function = "nand"; | |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| }; | |
| gmi_ad14_ph6 { | |
| nvidia,pins = "gmi_ad14_ph6"; | |
| nvidia,function = "nand"; | |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| }; | |
| gmi_wr_n_pi0 { | |
| nvidia,pins = "gmi_wr_n_pi0"; | |
| nvidia,function = "nand"; | |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| }; | |
| gmi_oe_n_pi1 { | |
| nvidia,pins = "gmi_oe_n_pi1"; | |
| nvidia,function = "nand"; | |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| }; | |
| gmi_dqs_pi2 { | |
| nvidia,pins = "gmi_dqs_pi2"; | |
| nvidia,function = "nand"; | |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| }; | |
| gmi_iordy_pi5 { | |
| nvidia,pins = "gmi_iordy_pi5"; | |
| nvidia,function = "rsvd1"; | |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| }; | |
| gmi_cs7_n_pi6 { | |
| nvidia,pins = "gmi_cs7_n_pi6"; | |
| nvidia,function = "nand"; | |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| }; | |
| gmi_wait_pi7 { | |
| nvidia,pins = "gmi_wait_pi7"; | |
| nvidia,function = "nand"; | |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| }; | |
| lcd_de_pj1 { | |
| nvidia,pins = "lcd_de_pj1"; | |
| nvidia,function = "displaya"; | |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| }; | |
| gmi_cs1_n_pj2 { | |
| nvidia,pins = "gmi_cs1_n_pj2"; | |
| nvidia,function = "rsvd1"; | |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| }; | |
| lcd_hsync_pj3 { | |
| nvidia,pins = "lcd_hsync_pj3"; | |
| nvidia,function = "displaya"; | |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| }; | |
| lcd_vsync_pj4 { | |
| nvidia,pins = "lcd_vsync_pj4"; | |
| nvidia,function = "displaya"; | |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| }; | |
| uart2_cts_n_pj5 { | |
| nvidia,pins = "uart2_cts_n_pj5"; | |
| nvidia,function = "uartb"; | |
| nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| }; | |
| uart2_rts_n_pj6 { | |
| nvidia,pins = "uart2_rts_n_pj6"; | |
| nvidia,function = "uartb"; | |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| }; | |
| gmi_a16_pj7 { | |
| nvidia,pins = "gmi_a16_pj7"; | |
| nvidia,function = "spi4"; | |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| }; | |
| gmi_adv_n_pk0 { | |
| nvidia,pins = "gmi_adv_n_pk0"; | |
| nvidia,function = "nand"; | |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| }; | |
| gmi_clk_pk1 { | |
| nvidia,pins = "gmi_clk_pk1"; | |
| nvidia,function = "nand"; | |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| }; | |
| gmi_cs2_n_pk3 { | |
| nvidia,pins = "gmi_cs2_n_pk3"; | |
| nvidia,function = "rsvd1"; | |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| }; | |
| gmi_cs3_n_pk4 { | |
| nvidia,pins = "gmi_cs3_n_pk4"; | |
| nvidia,function = "nand"; | |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| }; | |
| spdif_out_pk5 { | |
| nvidia,pins = "spdif_out_pk5"; | |
| nvidia,function = "spdif"; | |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| }; | |
| spdif_in_pk6 { | |
| nvidia,pins = "spdif_in_pk6"; | |
| nvidia,function = "spdif"; | |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| }; | |
| gmi_a19_pk7 { | |
| nvidia,pins = "gmi_a19_pk7"; | |
| nvidia,function = "spi4"; | |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| }; | |
| vi_d2_pl0 { | |
| nvidia,pins = "vi_d2_pl0"; | |
| nvidia,function = "sdmmc2"; | |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| }; | |
| vi_d3_pl1 { | |
| nvidia,pins = "vi_d3_pl1"; | |
| nvidia,function = "sdmmc2"; | |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| }; | |
| vi_d4_pl2 { | |
| nvidia,pins = "vi_d4_pl2"; | |
| nvidia,function = "vi"; | |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| }; | |
| vi_d5_pl3 { | |
| nvidia,pins = "vi_d5_pl3"; | |
| nvidia,function = "sdmmc2"; | |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| }; | |
| vi_d6_pl4 { | |
| nvidia,pins = "vi_d6_pl4"; | |
| nvidia,function = "vi"; | |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| }; | |
| vi_d7_pl5 { | |
| nvidia,pins = "vi_d7_pl5"; | |
| nvidia,function = "sdmmc2"; | |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| }; | |
| vi_d8_pl6 { | |
| nvidia,pins = "vi_d8_pl6"; | |
| nvidia,function = "sdmmc2"; | |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| }; | |
| vi_d9_pl7 { | |
| nvidia,pins = "vi_d9_pl7"; | |
| nvidia,function = "sdmmc2"; | |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| }; | |
| lcd_d16_pm0 { | |
| nvidia,pins = "lcd_d16_pm0"; | |
| nvidia,function = "displaya"; | |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| }; | |
| lcd_d17_pm1 { | |
| nvidia,pins = "lcd_d17_pm1"; | |
| nvidia,function = "displaya"; | |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| }; | |
| lcd_d18_pm2 { | |
| nvidia,pins = "lcd_d18_pm2"; | |
| nvidia,function = "displaya"; | |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| }; | |
| lcd_d19_pm3 { | |
| nvidia,pins = "lcd_d19_pm3"; | |
| nvidia,function = "displaya"; | |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| }; | |
| lcd_d20_pm4 { | |
| nvidia,pins = "lcd_d20_pm4"; | |
| nvidia,function = "displaya"; | |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| }; | |
| lcd_d21_pm5 { | |
| nvidia,pins = "lcd_d21_pm5"; | |
| nvidia,function = "displaya"; | |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| }; | |
| lcd_d22_pm6 { | |
| nvidia,pins = "lcd_d22_pm6"; | |
| nvidia,function = "displaya"; | |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| }; | |
| lcd_d23_pm7 { | |
| nvidia,pins = "lcd_d23_pm7"; | |
| nvidia,function = "displaya"; | |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| }; | |
| dap1_fs_pn0 { | |
| nvidia,pins = "dap1_fs_pn0"; | |
| nvidia,function = "i2s0"; | |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| }; | |
| dap1_din_pn1 { | |
| nvidia,pins = "dap1_din_pn1"; | |
| nvidia,function = "i2s0"; | |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| }; | |
| dap1_dout_pn2 { | |
| nvidia,pins = "dap1_dout_pn2"; | |
| nvidia,function = "i2s0"; | |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| }; | |
| dap1_sclk_pn3 { | |
| nvidia,pins = "dap1_sclk_pn3"; | |
| nvidia,function = "i2s0"; | |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| }; | |
| lcd_cs0_n_pn4 { | |
| nvidia,pins = "lcd_cs0_n_pn4"; | |
| nvidia,function = "displaya"; | |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| }; | |
| lcd_sdout_pn5 { | |
| nvidia,pins = "lcd_sdout_pn5"; | |
| nvidia,function = "displaya"; | |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| }; | |
| lcd_dc0_pn6 { | |
| nvidia,pins = "lcd_dc0_pn6"; | |
| nvidia,function = "displaya"; | |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| }; | |
| hdmi_int_pn7 { | |
| nvidia,pins = "hdmi_int_pn7"; | |
| nvidia,function = "hdmi"; | |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| }; | |
| ulpi_data7_po0 { | |
| nvidia,pins = "ulpi_data7_po0"; | |
| nvidia,function = "uarta"; | |
| nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| }; | |
| ulpi_data0_po1 { | |
| nvidia,pins = "ulpi_data0_po1"; | |
| nvidia,function = "uarta"; | |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| }; | |
| ulpi_data1_po2 { | |
| nvidia,pins = "ulpi_data1_po2"; | |
| nvidia,function = "uarta"; | |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| }; | |
| ulpi_data2_po3 { | |
| nvidia,pins = "ulpi_data2_po3"; | |
| nvidia,function = "uarta"; | |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| }; | |
| ulpi_data3_po4 { | |
| nvidia,pins = "ulpi_data3_po4"; | |
| nvidia,function = "uarta"; | |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| }; | |
| ulpi_data4_po5 { | |
| nvidia,pins = "ulpi_data4_po5"; | |
| nvidia,function = "uarta"; | |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| }; | |
| ulpi_data5_po6 { | |
| nvidia,pins = "ulpi_data5_po6"; | |
| nvidia,function = "uarta"; | |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| }; | |
| ulpi_data6_po7 { | |
| nvidia,pins = "ulpi_data6_po7"; | |
| nvidia,function = "uarta"; | |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| }; | |
| dap3_fs_pp0 { | |
| nvidia,pins = "dap3_fs_pp0"; | |
| nvidia,function = "i2s2"; | |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| }; | |
| dap3_din_pp1 { | |
| nvidia,pins = "dap3_din_pp1"; | |
| nvidia,function = "i2s2"; | |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| }; | |
| dap3_dout_pp2 { | |
| nvidia,pins = "dap3_dout_pp2"; | |
| nvidia,function = "i2s2"; | |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| }; | |
| dap3_sclk_pp3 { | |
| nvidia,pins = "dap3_sclk_pp3"; | |
| nvidia,function = "i2s2"; | |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| }; | |
| dap4_fs_pp4 { | |
| nvidia,pins = "dap4_fs_pp4"; | |
| nvidia,function = "i2s3"; | |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| }; | |
| dap4_din_pp5 { | |
| nvidia,pins = "dap4_din_pp5"; | |
| nvidia,function = "i2s3"; | |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| }; | |
| dap4_dout_pp6 { | |
| nvidia,pins = "dap4_dout_pp6"; | |
| nvidia,function = "i2s3"; | |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| }; | |
| dap4_sclk_pp7 { | |
| nvidia,pins = "dap4_sclk_pp7"; | |
| nvidia,function = "i2s3"; | |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| }; | |
| kb_col0_pq0 { | |
| nvidia,pins = "kb_col0_pq0"; | |
| nvidia,function = "kbc"; | |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| }; | |
| kb_col1_pq1 { | |
| nvidia,pins = "kb_col1_pq1"; | |
| nvidia,function = "kbc"; | |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| }; | |
| kb_col2_pq2 { | |
| nvidia,pins = "kb_col2_pq2"; | |
| nvidia,function = "kbc"; | |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| }; | |
| kb_col3_pq3 { | |
| nvidia,pins = "kb_col3_pq3"; | |
| nvidia,function = "kbc"; | |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| }; | |
| kb_col4_pq4 { | |
| nvidia,pins = "kb_col4_pq4"; | |
| nvidia,function = "kbc"; | |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| }; | |
| kb_col5_pq5 { | |
| nvidia,pins = "kb_col5_pq5"; | |
| nvidia,function = "kbc"; | |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| }; | |
| kb_col6_pq6 { | |
| nvidia,pins = "kb_col6_pq6"; | |
| nvidia,function = "kbc"; | |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| }; | |
| kb_col7_pq7 { | |
| nvidia,pins = "kb_col7_pq7"; | |
| nvidia,function = "kbc"; | |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| }; | |
| kb_row0_pr0 { | |
| nvidia,pins = "kb_row0_pr0"; | |
| nvidia,function = "kbc"; | |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| }; | |
| kb_row1_pr1 { | |
| nvidia,pins = "kb_row1_pr1"; | |
| nvidia,function = "kbc"; | |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| }; | |
| kb_row2_pr2 { | |
| nvidia,pins = "kb_row2_pr2"; | |
| nvidia,function = "kbc"; | |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| }; | |
| kb_row3_pr3 { | |
| nvidia,pins = "kb_row3_pr3"; | |
| nvidia,function = "kbc"; | |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| }; | |
| kb_row4_pr4 { | |
| nvidia,pins = "kb_row4_pr4"; | |
| nvidia,function = "kbc"; | |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| }; | |
| kb_row5_pr5 { | |
| nvidia,pins = "kb_row5_pr5"; | |
| nvidia,function = "kbc"; | |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| }; | |
| kb_row6_pr6 { | |
| nvidia,pins = "kb_row6_pr6"; | |
| nvidia,function = "kbc"; | |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| }; | |
| kb_row7_pr7 { | |
| nvidia,pins = "kb_row7_pr7"; | |
| nvidia,function = "kbc"; | |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| }; | |
| kb_row8_ps0 { | |
| nvidia,pins = "kb_row8_ps0"; | |
| nvidia,function = "kbc"; | |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| }; | |
| kb_row9_ps1 { | |
| nvidia,pins = "kb_row9_ps1"; | |
| nvidia,function = "kbc"; | |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| }; | |
| kb_row10_ps2 { | |
| nvidia,pins = "kb_row10_ps2"; | |
| nvidia,function = "kbc"; | |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| }; | |
| kb_row11_ps3 { | |
| nvidia,pins = "kb_row11_ps3"; | |
| nvidia,function = "kbc"; | |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| }; | |
| kb_row12_ps4 { | |
| nvidia,pins = "kb_row12_ps4"; | |
| nvidia,function = "kbc"; | |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| }; | |
| kb_row13_ps5 { | |
| nvidia,pins = "kb_row13_ps5"; | |
| nvidia,function = "kbc"; | |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| }; | |
| kb_row14_ps6 { | |
| nvidia,pins = "kb_row14_ps6"; | |
| nvidia,function = "kbc"; | |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| }; | |
| kb_row15_ps7 { | |
| nvidia,pins = "kb_row15_ps7"; | |
| nvidia,function = "kbc"; | |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| }; | |
| vi_pclk_pt0 { | |
| nvidia,pins = "vi_pclk_pt0"; | |
| nvidia,function = "rsvd1"; | |
| nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
| nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| }; | |
| vi_mclk_pt1 { | |
| nvidia,pins = "vi_mclk_pt1"; | |
| nvidia,function = "vi"; | |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| }; | |
| vi_d10_pt2 { | |
| nvidia,pins = "vi_d10_pt2"; | |
| nvidia,function = "ddr"; | |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| }; | |
| vi_d11_pt3 { | |
| nvidia,pins = "vi_d11_pt3"; | |
| nvidia,function = "ddr"; | |
| nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
| nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| }; | |
| vi_d0_pt4 { | |
| nvidia,pins = "vi_d0_pt4"; | |
| nvidia,function = "ddr"; | |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| }; | |
| gen2_i2c_scl_pt5 { | |
| nvidia,pins = "gen2_i2c_scl_pt5"; | |
| nvidia,function = "i2c2"; | |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
| }; | |
| gen2_i2c_sda_pt6 { | |
| nvidia,pins = "gen2_i2c_sda_pt6"; | |
| nvidia,function = "i2c2"; | |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
| }; | |
| pu0 { | |
| nvidia,pins = "pu0"; | |
| nvidia,function = "owr"; | |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| }; | |
| pu1 { | |
| nvidia,pins = "pu1"; | |
| nvidia,function = "rsvd1"; | |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| }; | |
| pu2 { | |
| nvidia,pins = "pu2"; | |
| nvidia,function = "rsvd1"; | |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| }; | |
| pu3 { | |
| nvidia,pins = "pu3"; | |
| nvidia,function = "pwm0"; | |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| }; | |
| pu4 { | |
| nvidia,pins = "pu4"; | |
| nvidia,function = "pwm1"; | |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| }; | |
| pu5 { | |
| nvidia,pins = "pu5"; | |
| nvidia,function = "rsvd4"; | |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| }; | |
| pu6 { | |
| nvidia,pins = "pu6"; | |
| nvidia,function = "pwm3"; | |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| }; | |
| jtag_rtck_pu7 { | |
| nvidia,pins = "jtag_rtck_pu7"; | |
| nvidia,function = "rtck"; | |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| }; | |
| pv0 { | |
| nvidia,pins = "pv0"; | |
| nvidia,function = "rsvd1"; | |
| nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
| nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| }; | |
| pv1 { | |
| nvidia,pins = "pv1"; | |
| nvidia,function = "rsvd1"; | |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| }; | |
| pv2 { | |
| nvidia,pins = "pv2"; | |
| nvidia,function = "owr"; | |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| }; | |
| pv3 { | |
| nvidia,pins = "pv3"; | |
| nvidia,function = "clk_12m_out"; | |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| }; | |
| ddc_scl_pv4 { | |
| nvidia,pins = "ddc_scl_pv4"; | |
| nvidia,function = "i2c4"; | |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| }; | |
| ddc_sda_pv5 { | |
| nvidia,pins = "ddc_sda_pv5"; | |
| nvidia,function = "i2c4"; | |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| }; | |
| crt_hsync_pv6 { | |
| nvidia,pins = "crt_hsync_pv6"; | |
| nvidia,function = "crt"; | |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| }; | |
| crt_vsync_pv7 { | |
| nvidia,pins = "crt_vsync_pv7"; | |
| nvidia,function = "crt"; | |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| }; | |
| lcd_cs1_n_pw0 { | |
| nvidia,pins = "lcd_cs1_n_pw0"; | |
| nvidia,function = "displaya"; | |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| }; | |
| lcd_m1_pw1 { | |
| nvidia,pins = "lcd_m1_pw1"; | |
| nvidia,function = "displaya"; | |
| nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| }; | |
| spi2_cs1_n_pw2 { | |
| nvidia,pins = "spi2_cs1_n_pw2"; | |
| nvidia,function = "spi2"; | |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| }; | |
| clk1_out_pw4 { | |
| nvidia,pins = "clk1_out_pw4"; | |
| nvidia,function = "extperiph1"; | |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| }; | |
| clk2_out_pw5 { | |
| nvidia,pins = "clk2_out_pw5"; | |
| nvidia,function = "extperiph2"; | |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| }; | |
| uart3_txd_pw6 { | |
| nvidia,pins = "uart3_txd_pw6"; | |
| nvidia,function = "uartc"; | |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| }; | |
| uart3_rxd_pw7 { | |
| nvidia,pins = "uart3_rxd_pw7"; | |
| nvidia,function = "uartc"; | |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| }; | |
| spi2_sck_px2 { | |
| nvidia,pins = "spi2_sck_px2"; | |
| nvidia,function = "gmi"; | |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| }; | |
| spi1_mosi_px4 { | |
| nvidia,pins = "spi1_mosi_px4"; | |
| nvidia,function = "spi1"; | |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| }; | |
| spi1_sck_px5 { | |
| nvidia,pins = "spi1_sck_px5"; | |
| nvidia,function = "spi1"; | |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| }; | |
| spi1_cs0_n_px6 { | |
| nvidia,pins = "spi1_cs0_n_px6"; | |
| nvidia,function = "spi1"; | |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| }; | |
| spi1_miso_px7 { | |
| nvidia,pins = "spi1_miso_px7"; | |
| nvidia,function = "spi1"; | |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| }; | |
| ulpi_clk_py0 { | |
| nvidia,pins = "ulpi_clk_py0"; | |
| nvidia,function = "uartd"; | |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| }; | |
| ulpi_dir_py1 { | |
| nvidia,pins = "ulpi_dir_py1"; | |
| nvidia,function = "uartd"; | |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| }; | |
| ulpi_nxt_py2 { | |
| nvidia,pins = "ulpi_nxt_py2"; | |
| nvidia,function = "uartd"; | |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| }; | |
| ulpi_stp_py3 { | |
| nvidia,pins = "ulpi_stp_py3"; | |
| nvidia,function = "uartd"; | |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| }; | |
| sdmmc1_dat3_py4 { | |
| nvidia,pins = "sdmmc1_dat3_py4"; | |
| nvidia,function = "sdmmc1"; | |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| }; | |
| sdmmc1_dat2_py5 { | |
| nvidia,pins = "sdmmc1_dat2_py5"; | |
| nvidia,function = "sdmmc1"; | |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| }; | |
| sdmmc1_dat1_py6 { | |
| nvidia,pins = "sdmmc1_dat1_py6"; | |
| nvidia,function = "sdmmc1"; | |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| }; | |
| sdmmc1_dat0_py7 { | |
| nvidia,pins = "sdmmc1_dat0_py7"; | |
| nvidia,function = "sdmmc1"; | |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| }; | |
| sdmmc1_clk_pz0 { | |
| nvidia,pins = "sdmmc1_clk_pz0"; | |
| nvidia,function = "sdmmc1"; | |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| }; | |
| sdmmc1_cmd_pz1 { | |
| nvidia,pins = "sdmmc1_cmd_pz1"; | |
| nvidia,function = "sdmmc1"; | |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| }; | |
| lcd_sdin_pz2 { | |
| nvidia,pins = "lcd_sdin_pz2"; | |
| nvidia,function = "displaya"; | |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| }; | |
| lcd_wr_n_pz3 { | |
| nvidia,pins = "lcd_wr_n_pz3"; | |
| nvidia,function = "displaya"; | |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| }; | |
| lcd_sck_pz4 { | |
| nvidia,pins = "lcd_sck_pz4"; | |
| nvidia,function = "displaya"; | |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| }; | |
| sys_clk_req_pz5 { | |
| nvidia,pins = "sys_clk_req_pz5"; | |
| nvidia,function = "sysclk"; | |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| }; | |
| pwr_i2c_scl_pz6 { | |
| nvidia,pins = "pwr_i2c_scl_pz6"; | |
| nvidia,function = "i2cpwr"; | |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| nvidia,open-drain = <TEGRA_PIN_ENABLE>; | |
| }; | |
| pwr_i2c_sda_pz7 { | |
| nvidia,pins = "pwr_i2c_sda_pz7"; | |
| nvidia,function = "i2cpwr"; | |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| nvidia,open-drain = <TEGRA_PIN_ENABLE>; | |
| }; | |
| pbb0 { | |
| nvidia,pins = "pbb0"; | |
| nvidia,function = "i2s4"; | |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| }; | |
| cam_i2c_scl_pbb1 { | |
| nvidia,pins = "cam_i2c_scl_pbb1"; | |
| nvidia,function = "i2c3"; | |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
| }; | |
| cam_i2c_sda_pbb2 { | |
| nvidia,pins = "cam_i2c_sda_pbb2"; | |
| nvidia,function = "i2c3"; | |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
| }; | |
| pbb3 { | |
| nvidia,pins = "pbb3"; | |
| nvidia,function = "vgp3"; | |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| }; | |
| pbb4 { | |
| nvidia,pins = "pbb4"; | |
| nvidia,function = "vgp4"; | |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| }; | |
| pbb5 { | |
| nvidia,pins = "pbb5"; | |
| nvidia,function = "vgp5"; | |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| }; | |
| pbb6 { | |
| nvidia,pins = "pbb6"; | |
| nvidia,function = "vgp6"; | |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| }; | |
| pbb7 { | |
| nvidia,pins = "pbb7"; | |
| nvidia,function = "i2s4"; | |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| }; | |
| pcc1 { | |
| nvidia,pins = "pcc1"; | |
| nvidia,function = "i2s4"; | |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| }; | |
| pcc2 { | |
| nvidia,pins = "pcc2"; | |
| nvidia,function = "i2s4"; | |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| }; | |
| clk2_req_pcc5 { | |
| nvidia,pins = "clk2_req_pcc5"; | |
| nvidia,function = "dap"; | |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| }; | |
| pex_l2_rst_n_pcc6 { | |
| nvidia,pins = "pex_l2_rst_n_pcc6"; | |
| nvidia,function = "pcie"; | |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| }; | |
| pex_l2_clkreq_n_pcc7 { | |
| nvidia,pins = "pex_l2_clkreq_n_pcc7"; | |
| nvidia,function = "pcie"; | |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| }; | |
| pex_l0_prsnt_n_pdd0 { | |
| nvidia,pins = "pex_l0_prsnt_n_pdd0"; | |
| nvidia,function = "pcie"; | |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| }; | |
| pex_l0_rst_n_pdd1 { | |
| nvidia,pins = "pex_l0_rst_n_pdd1"; | |
| nvidia,function = "pcie"; | |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| }; | |
| pex_l0_clkreq_n_pdd2 { | |
| nvidia,pins = "pex_l0_clkreq_n_pdd2"; | |
| nvidia,function = "pcie"; | |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| }; | |
| pex_wake_n_pdd3 { | |
| nvidia,pins = "pex_wake_n_pdd3"; | |
| nvidia,function = "pcie"; | |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| }; | |
| pex_l1_prsnt_n_pdd4 { | |
| nvidia,pins = "pex_l1_prsnt_n_pdd4"; | |
| nvidia,function = "pcie"; | |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| }; | |
| pex_l1_rst_n_pdd5 { | |
| nvidia,pins = "pex_l1_rst_n_pdd5"; | |
| nvidia,function = "pcie"; | |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| }; | |
| pex_l1_clkreq_n_pdd6 { | |
| nvidia,pins = "pex_l1_clkreq_n_pdd6"; | |
| nvidia,function = "pcie"; | |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| }; | |
| pex_l2_prsnt_n_pdd7 { | |
| nvidia,pins = "pex_l2_prsnt_n_pdd7"; | |
| nvidia,function = "pcie"; | |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| }; | |
| clk3_out_pee0 { | |
| nvidia,pins = "clk3_out_pee0"; | |
| nvidia,function = "extperiph3"; | |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| }; | |
| clk3_req_pee1 { | |
| nvidia,pins = "clk3_req_pee1"; | |
| nvidia,function = "dev3"; | |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| }; | |
| clk1_req_pee2 { | |
| nvidia,pins = "clk1_req_pee2"; | |
| nvidia,function = "dap"; | |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| }; | |
| hdmi_cec_pee3 { | |
| nvidia,pins = "hdmi_cec_pee3"; | |
| nvidia,function = "cec"; | |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
| }; | |
| owr { | |
| nvidia,pins = "owr"; | |
| nvidia,function = "owr"; | |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| }; | |
| /* SDMMC4 pinmux */ | |
| sdmmc4_clk { | |
| nvidia,pins = "sdmmc4_clk_pcc4"; | |
| nvidia,function = "sdmmc4"; | |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| nvidia,lock = <TEGRA_PIN_DISABLE>; | |
| nvidia,io-reset = <TEGRA_PIN_DISABLE>; | |
| }; | |
| sdmmc4_cmd { | |
| nvidia,pins = "sdmmc4_cmd_pt7", | |
| "sdmmc4_dat0_paa0", | |
| "sdmmc4_dat1_paa1", | |
| "sdmmc4_dat2_paa2", | |
| "sdmmc4_dat3_paa3", | |
| "sdmmc4_dat4_paa4", | |
| "sdmmc4_dat5_paa5", | |
| "sdmmc4_dat6_paa6", | |
| "sdmmc4_dat7_paa7"; | |
| nvidia,function = "sdmmc4"; | |
| nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
| nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| nvidia,lock = <TEGRA_PIN_DISABLE>; | |
| nvidia,io-reset = <TEGRA_PIN_DISABLE>; | |
| }; | |
| sdmmc4_rst_n { | |
| nvidia,pins = "sdmmc4_rst_n_pcc3"; | |
| nvidia,function = "rsvd2"; | |
| nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
| nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| }; | |
| cam_mclk { | |
| nvidia,pins = "cam_mclk_pcc0"; | |
| nvidia,function = "vi_alt3"; | |
| nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
| nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| }; | |
| drive_groups { | |
| nvidia,pins = "drive_gma", | |
| "drive_gmb", | |
| "drive_gmc", | |
| "drive_gmd"; | |
| nvidia,pull-down-strength = <9>; | |
| nvidia,pull-up-strength = <9>; | |
| nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_SLOWEST>; | |
| nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_SLOWEST>; | |
| }; | |
| }; | |
| }; | |
| uartd: serial@70006300 { | |
| status = "okay"; | |
| }; | |
| hdmi_ddc: i2c@7000c700 { | |
| status = "okay"; | |
| clock-frequency = <100000>; | |
| }; | |
| pwr_i2c: i2c@7000d000 { | |
| status = "okay"; | |
| clock-frequency = <400000>; | |
| pmic: pmic@2d { | |
| compatible = "ti,tps65911"; | |
| reg = <0x2d>; | |
| interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; | |
| #interrupt-cells = <2>; | |
| interrupt-controller; | |
| wakeup-source; | |
| ti,en-gpio-sleep = <0 1 1 1 1 1 0 0 1>; | |
| ti,system-power-controller; | |
| ti,sleep-keep-ck32k; | |
| ti,sleep-enable; | |
| #gpio-cells = <2>; | |
| gpio-controller; | |
| regulators { | |
| vdd_1v8: vddio { | |
| regulator-name = "vdd_1v8_gen"; | |
| regulator-min-microvolt = <1800000>; | |
| regulator-max-microvolt = <1800000>; | |
| regulator-always-on; | |
| regulator-boot-on; | |
| }; | |
| ldo7_reg: ldo7 { | |
| regulator-name = "vdd_pllm,x,u,a_p_c_s"; | |
| regulator-min-microvolt = <1200000>; | |
| regulator-max-microvolt = <1200000>; | |
| regulator-boot-on; | |
| }; | |
| }; | |
| }; | |
| }; | |
| sdmmc4: mmc@78000600 { | |
| status = "okay"; | |
| bus-width = <8>; | |
| non-removable; | |
| vmmc-supply = <&sys_3v3_reg>; | |
| vqmmc-supply = <&vdd_1v8>; | |
| }; | |
| micro_usb: usb@7d000000 { | |
| status = "okay"; | |
| dr_mode = "otg"; | |
| }; | |
| usb-phy@7d000000 { | |
| status = "okay"; | |
| }; | |
| ethernet_usb: usb@7d004000 { | |
| status = "okay"; | |
| nvidia,vbus-gpio = <&gpio TEGRA_GPIO(DD, 5) GPIO_ACTIVE_HIGH>; | |
| #address-cells = <1>; | |
| #size-cells = <0>; | |
| /* SMSC 10/100T Ethernet Controller */ | |
| ethernet@2 { | |
| compatible = "usb424,9e00"; | |
| reg = <2>; | |
| local-mac-address = [00 11 22 33 44 55]; | |
| }; | |
| }; | |
| usb-phy@7d004000 { | |
| status = "okay"; | |
| }; | |
| fullsize_usb: usb@7d008000 { | |
| status = "okay"; | |
| nvidia,vbus-gpio = <&gpio TEGRA_GPIO(DD, 4) GPIO_ACTIVE_HIGH>; | |
| }; | |
| usb-phy@7d008000 { | |
| status = "okay"; | |
| }; | |
| /* PMIC has a built-in 32KHz oscillator which is used by PMC */ | |
| clk32k_in: clock { | |
| compatible = "fixed-clock"; | |
| #clock-cells = <0>; | |
| clock-frequency = <32768>; | |
| clock-output-names = "pmic-oscillator"; | |
| }; | |
| gpio-keys { | |
| compatible = "gpio-keys"; | |
| key-power { | |
| label = "Power"; | |
| gpios = <&gpio TEGRA_GPIO(V, 0) GPIO_ACTIVE_LOW>; | |
| linux,code = <KEY_POWER>; | |
| }; | |
| }; | |
| leds { | |
| compatible = "gpio-leds"; | |
| led-power { | |
| label = "power-led"; | |
| gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_HIGH>; | |
| default-state = "on"; | |
| linux,default-trigger = "heartbeat"; | |
| retain-state-suspended; | |
| }; | |
| }; | |
| sys_3v3_reg: regulator-sys-3v3 { | |
| compatible = "regulator-fixed"; | |
| regulator-name = "sys_3v3"; | |
| regulator-min-microvolt = <3300000>; | |
| regulator-max-microvolt = <3300000>; | |
| regulator-always-on; | |
| regulator-boot-on; | |
| }; | |
| vdd_vid_reg: regulator-vdd-vid { | |
| compatible = "regulator-fixed"; | |
| regulator-name = "vddio_vid"; | |
| regulator-min-microvolt = <5000000>; | |
| regulator-max-microvolt = <5000000>; | |
| regulator-boot-on; | |
| gpio = <&gpio TEGRA_GPIO(T, 0) GPIO_ACTIVE_HIGH>; | |
| enable-active-high; | |
| }; | |
| }; |