blob: 1a31c11bc3b43765fc8dc4ee51f0b9c87968437f [file] [edit]
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/soc/renesas/renesas,rzn1-gpioirqmux.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Renesas RZ/N1 SoCs GPIO Interrupt Multiplexer
description: |
The Renesas RZ/N1 GPIO Interrupt Multiplexer multiplexes GPIO interrupt
lines to the interrupt controller available in the SoC.
It selects up to 8 of the 96 GPIO interrupt lines available and connect them
to 8 output interrupt lines.
maintainers:
- Herve Codina <herve.codina@bootlin.com>
properties:
compatible:
items:
- enum:
- renesas,r9a06g032-gpioirqmux
- const: renesas,rzn1-gpioirqmux
reg:
maxItems: 1
"#address-cells":
const: 0
"#interrupt-cells":
const: 1
interrupt-map-mask:
items:
- const: 0x7f
interrupt-map:
description: |
Specifies the mapping from external GPIO interrupt lines to the output
interrupts. The array has up to 8 items defining the mapping related to
the output line 0 (GIC 103) up to the output line 7 (GIC 110).
The child interrupt number set in arrays items is computed using the
following formula:
gpio_bank * 32 + gpio_number
with:
- gpio_bank: The GPIO bank number
- 0 for GPIO0A,
- 1 for GPIO1A,
- 2 for GPIO2A
- gpio_number: Number of the gpio in the bank (0..31)
minItems: 1
maxItems: 8
required:
- compatible
- reg
- "#address-cells"
- "#interrupt-cells"
- interrupt-map-mask
- interrupt-map
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
gic: interrupt-controller {
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <3>;
};
interrupt-controller@51000480 {
compatible = "renesas,r9a06g032-gpioirqmux", "renesas,rzn1-gpioirqmux";
reg = <0x51000480 0x20>;
#address-cells = <0>;
#interrupt-cells = <1>;
interrupt-map-mask = <0x7f>;
interrupt-map =
<32 &gic GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, /* line 0, GPIO1A.0 */
<89 &gic GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, /* line 1, GPIO2A.25 */
<9 &gic GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; /* line 3, GPIO0A.9 */
};